Semiconductor memory devices including subword driver and layouts thereof

Patent metadata

Field	Value
Publication number	US-11450375-B2
Application number	US-202017006730-A
Country	US
Kind code	B2
Filing date	Aug 28, 2020
Priority date	Aug 28, 2020
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

In some examples, a subword driver block of a memory device includes a plurality of active regions of a first type and a plurality of active regions of a second type adjacent to the plurality of active regions of the first type. The subword driver block further includes a plurality of first gate electrodes overlapping with the plurality of active regions of the first type to form a plurality of first transistors, and a plurality of second gate electrodes overlapping with the plurality of active regions of the first type to form a plurality of second transistors. Each of the second transistors is shared by a first subword driver and a second subword driver. Each of the second transistors may include a drain and a source respectively coupled to a first and second word line, which are driven by the first subword driver and the second subword driver, respectively.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first area of a subword driver block, the first area comprising:
a first active region;
a plurality of first transistors formed on the first active region, each of the transistors including:
a gate; and
drain and source disposed on opposite sides of the gate, respectively, in a plan view, wherein one of the drain and source is coupled to an output of a first corresponding one of subword drivers and the other of the drain and source is coupled to an output of a second corresponding one of the subword drivers; and

a plurality of gate electrodes overlapping with the first active region to form a plurality of second transistors,
wherein a first transistor from the plurality of first transistors is positioned between a second transistor from the plurality of second transistors and a third transistor from the plurality of second transistors, wherein the gates of the second and third transistors comprise a first gate electrode and a second gate electrode from the plurality of gate electrodes, respectively,
wherein the first gate electrode is coupled to a first main word line and the second gate electrode is coupled to a second main word line,
wherein the first transistor and the second transistor are adjacent to each other to share a first contact coupled to a first word line of the memory cell array and the first transistor and the third transistor are adjacent to each other to share a second contact coupled to a second word line of the memory cell array, and
wherein a fourth transistor from the plurality of second transistors is adjacent to the second transistor to share a third contact with the second transistor, and wherein the third contact is coupled to a non-active potential.

2. The semiconductor of claim 1 , further comprising a second area of a subword driver block, the second area adjacent to the first active region and comprising:
a second active region; and
a plurality of third transistors formed on the second active region and a respective gate electrode of the plurality of gate electrodes,
wherein the first transistors and the second transistors are of a first conductivity type and the third transistors are of a second conductivity type.

3. The semiconductor of claim 2 , wherein the first conductivity type is an n-channel type and the second conductivity type is a p-channel type.

4. A semiconductor device comprising:
a first area of a subword driver block, the first area comprising:
a first active region;
a plurality of first transistors formed on the first active region, each of the transistors including:
a gate; and
drain and source disposed on opposite sides of the gate, respectively, in a plan view, wherein one of the drain and source is coupled to an output of a first corresponding one of subword drivers and the other of the drain and source is coupled to an output of a second corresponding one of the subword drivers; and

a plurality of gate electrodes overlapping with the first active region to form a plurality of second transistors; and

a second area of a subword driver block, the second area adjacent to the first active region and comprising:
a second active region;
a plurality of third transistors formed on the second active region and a respective gate electrode of the plurality of gate electrodes, wherein the first transistors and the second transistors are of a first conductivity type and the third transistors are of a second conductivity type, wherein the first conductivity type is an n-channel type and the second conductivity type is a p-channel type; and
a first sub-region and a second sub-region, wherein the first area is disposed between the first and second sub-regions of the second region of the second area.

5. A semiconductor device comprising:
a first area of a subword driver block, the first area comprising:
a first active region;
a plurality of first transistors formed on the first active region, each of the transistors including:
a gate; and
drain and source disposed on opposite sides of the gate, respectively, in a plan view, wherein one of the drain and source is coupled to an output of a first corresponding one of subword drivers and the other of the drain and source is coupled to an output of a second corresponding one of the subword drivers; and

a plurality of gate electrodes overlapping with the first active region to form a plurality of second transistors; and

a second area of a subword driver block, the second area adjacent to the first active region and comprising:
a second active region;
a plurality of third transistors formed on the second active region and a respective gate electrode of the plurality of gate electrodes, wherein the first transistors and the second transistors are of a first conductivity type and the third transistors are of a second conductivity type, wherein the first conductivity type is an n-channel type and the second conductivity type is a p-channel type,

wherein the first area further comprises a first sub-region and a second sub-region, wherein the second area is disposed between the first and second sub-regions of the first active region of the first area.

6. An apparatus comprising:
a plurality of active regions of a first type;
a plurality of first gate electrodes overlapping with the plurality of active regions of the first type to form a plurality of first transistors; and
a plurality of second gate electrodes overlapping with the plurality of active regions of the first type to form a plurality of second transistors, wherein each of the second gate electrodes is positioned between a respective first gate electrode and second gate electrode from the plurality of first gate electrodes,
wherein the first gate electrode and the second gate electrode from the plurality of first gate electrodes are coupled to a first and second main word line, respectively,
wherein an active region of the plurality of active regions defines a recess at a section at which a respective one of the second gate electrodes overlaps.

7. The apparatus of claim 6 , wherein the respective one of the second gate electrodes is coupled to a respective word driver line.

8. The apparatus of claim 6 , wherein the first and second transistors are of a same conductivity type.

9. The apparatus of claim 6 , wherein a transistor of the plurality of second transistors comprises drain and source regions in a respective one of the plurality of active regions of the first type, wherein the drain and source regions of the transistor are coupled to an output of a first subword driver and an output of a second subword driver, respectively.

10. An apparatus comprising:
a plurality of active regions of a first type;
a plurality of first gate electrodes overlapping with the plurality of active regions of the first type to form a plurality of first transistors; and
a plurality of second gate electrodes overlapping with the plurality of active regions of the first type to form a plurality of second transistors, wherein each of the second gate electrodes is positioned between a respective first gate electrode and second gate electrode from the plurality of first gate electrodes,
wherein the first gate electrode and the second gate electrode from the plurality of first gate electrodes are coupled to a first and second main word line, respectively, wherein a transistor of the plurality of first transistors comprises drain and source regions in a respective one of the plurality of active regions of the first type, wherein the drain and source regions of the transistor are coupled to a word line and non-active potential line, respectively.

11. An apparatus comprising:

Assignees

• Micron Technology Inc

Inventors

• SHIRAKO Takefumi
• Yokomichi Masahiro
• Lee Kyuseok
• Hwang Sangmin

Classifications

• G11C11/1697

  Power supply circuits · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C11/408

  Address circuits · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C11/4085 Primary

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title