Signal adjusting circuit and method and display device

Patent metadata

Field	Value
Publication number	US-11450256-B2
Application number	US-201817257009-A
Country	US
Kind code	B2
Filing date	Dec 13, 2018
Priority date	Oct 30, 2018
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

A signal adjusting circuit includes an identification circuit, an analysis circuit and an adjusting circuit; where the identification circuit is configured to acquire row data to be transmitted and identify the type of each data; the analysis circuit is connected with the identification circuit and is configured to analyze the data type of the row data according to the type of each data and output an adjusting instruction when the row data type meets or exceeds a preset data type criterion; the adjusting circuit is connected with the analysis circuit and is configured to adjust the transmission amplitude of the output data signal according to the adjusting instruction.

First claim

What is claimed is:

1. A signal adjusting circuit, comprising:
an identification circuit configured to acquire a row data that comprises a plurality of bits to be transmitted on a differential pair, and further configured to identify a type of each bit, wherein the bit type comprises 0 and 1, wherein the 0 represents a negative level and the 1 represents a positive level;
an analysis circuit coupled with the identification circuit and configured to analyze a data type of the row data based on the type of each bit, and output an adjusting instruction in the case where the row data type meets or exceeds a preset data type criterion; and
an adjusting circuit coupled with the analysis circuit and configured to adjust a transmission amplitude of an output data signal corresponding to the row data according to the adjusting instruction;
wherein the preset data type criterion comprises a forward preset data type criterion and a corresponding reverse preset data type criterion;
wherein the preset data type criterion is set according to a switching frequency of the data type;
wherein the differential pair comprises a first transmission line corresponding to the forward preset data type criterion and a second transmission line corresponding to the reverse preset data type criterion, and wherein when the row data type of the row data to be transmitted through the differential pair meets the preset data type criterion that the bit type is suddenly switched to 1 after a plurality of consecutive 0s or that the bit type is suddenly switched to 0 after a plurality of 1s, a transmission amplitude of each of the first transmission line and the second transmission line of the differential pair is increased.

2. The signal adjusting circuit of claim 1 , wherein the identification circuit comprises:
a storage device coupled with the analysis circuit and configured to acquire the row data to be transmitted and store or output the row data; and
a counting device coupled with the storage device and the analysis circuit and configured to count the plurality of bits contained in the row data and identify the type of each bit.

3. The signal adjusting circuit of claim 2 , wherein the storage device comprises a row memory.

4. The signal adjusting circuit of claim 2 , wherein the counting device comprises a column counter.

5. The signal adjusting circuit of claim 1 , wherein the analysis circuit comprises:
an analysis device coupled with the identification circuit and configured to analyze the row data type based on the type of each bit; and
a comparison device coupled with the analysis device and configured to compare the row data type against the preset data type criterion, and generate the adjusting instruction in the case where the row data type meets or exceeds the preset data type criterion.

6. The signal adjusting circuit of claim 1 , wherein the adjusting circuit comprises:
a current adjusting device coupled with the analysis circuit and configured to adjust an output current according to the adjusting instruction.

7. The signal adjusting circuit of claim 6 , wherein the current adjusting device is a current source.

8. The signal adjusting circuit of claim 1 , wherein the row data is a pixel data.

9. The signal adjusting circuit of claim 1 , wherein in the case where there are a plurality of consecutive same bits being transmitted on each of the first transmission line and the second transmission line of the differential pair, the row data is transmitted using a relatively low amplitude without adjustment on each of the first transmission line and the second transmission line of the differential pair.

10. The signal adjusting circuit of claim 1 , wherein an intersection point of a sloping switching curve of a first voltage level on the first transmission line with a corresponding reversely sloping switching curve of a second voltage level on the second transmission line after the adjustment of increasing the transmission amplitude of each of the first transmission line and the second transmission line is earlier in time than an intersection point of a sloping switching curve of the first voltage level on the first transmission line with a corresponding reversely sloping switching curve of the second voltage level on the second transmission line before the adjustment.

11. A display device comprising a display panel and a signal adjusting circuit coupled with the display panel;
wherein the signal adjusting circuit comprises:
an identification circuit configured to acquire a row data that comprises a plurality of bits to be transmitted on a differential pair, and further configured to identify a type of each bit, wherein the bit type comprises 0 and 1, wherein the 0 represents a negative level and the 1 represents a positive level;
an analysis circuit coupled with the identification circuit and configured to analyze a data type of the row data based on the type of each bit, and output an adjusting instruction in the case where the row data type meets or exceeds a preset data type criterion; and
an adjusting circuit coupled with the analysis circuit and configured to adjust a transmission amplitude of an output data signal corresponding to the row data according to the adjusting instruction;
wherein the preset data type criterion comprises a forward preset data type criterion and a corresponding reverse preset data type criterion;
wherein the preset data type criterion is set according to a switching frequency of the data type;
wherein the differential pair comprises a first transmission line corresponding to the forward preset data type criterion and a second transmission line corresponding to the reverse preset data type criterion, and wherein when the row data type of the row data to be transmitted through the differential pair meets the preset data type criterion that the bit type is suddenly switched to 1 after a plurality of consecutive 0s or that the bit type is suddenly switched to 0 after a plurality of 1s, a transmission amplitude of each of the first transmission line and the second transmission line of the differential pair is increased.

12. A signal adjusting method comprising:
acquiring a row data that comprises a plurality of bits to be transmitted on a differential pair, and identifying a type of each bit, wherein the bit type comprises 0 and 1, wherein the 0 represents a negative level and the 1 represents a positive level;
analyzing a data type of the row data based on the type of each bit, and outputting an adjusting instruction in the case where the row data type meets or exceeds the preset data type criterion; and
adjusting a transmission amplitude of an output data signal corresponding to the row data according to the adjusting instruction;
wherein the preset data type criterion comprises a forward preset data type criterion and a corresponding reverse preset data type criterion;
wherein the preset data type criterion is set according to a switching frequency of the data type;
wherein the differential pair comprises a first transmission line corresponding to the forward preset data type criterion and a second transmission line corresponding to the reverse preset data type criterion, and wherein when the row data type of the row data to be transmitted through the differential pair meets the preset data type criterion that the bit type is suddenly switched to 1 after a plurality of consecutive 0s or that the bit type is suddenly switched to 0 after a plurality of 1s, a transmission amplitude of each of the first transmission line and the second transmission line of the differential pair is increased.

13. The signal adjusting method of claim 12

Assignees

• Hkc Corp Ltd

Inventors

• Wang Mingliang

Classifications

• G09G3/3611 Primary

  Control of matrices with row and column drivers · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2330/06

  Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation · CPC title

• G09G2370/00

  Aspects of data communication · CPC title