Model calculation unit and control unit for calculating a multilayer perceptron model with feedforward and feedback

Patent metadata

Field	Value
Publication number	US-11449737-B2
Application number	US-201716330625-A
Country	US
Kind code	B2
Filing date	Sep 4, 2017
Priority date	Sep 7, 2016
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

A model calculation unit for calculating a multilayer perceptron model, the model calculation unit being designed in hardware and being hardwired, including: a process or core; a memory; a DMA unit, which is designed to successively instruct the processor core to calculate a neuron layer, in each case based on input variables of an assigned input variable vector and to store the respectively resulting output variables of an output variable vector in an assigned data memory section, the data memory section for the input variable vector assigned to at least one of the neuron layers at least partially including in each case the data memory sections of at least two of the output variable vectors of two different neuron layers.

First claim

What is claimed is:

1. A model calculation unit for calculating a multilayer perceptron model having a plurality of neuron layers, the model calculation unit being designed in hardware and being hardwired, the model calculation unit comprising:
a processor core which is configured to calculate one or multiple output variables of an output variable vector of a neuron layer of the multilayer perceptron model having a number of neurons as a function of one or of multiple input variables of an input variable vector;
a memory which a data memory area is provided, in which each neuron layer is assigned a data memory section for storing the input variables of the input variable vector and a data memory section for storing the output variables of the output variable vector; and
a DMA unit which is configured to successively instruct the processor core to calculate a neuron layer, in each case based on input variables of the assigned input variable vector and to store the respectively resulting output variables of the output variable vector in the assigned data memory section;
wherein the data memory section for the input variable vector assigned to at least one of the neuron layers at least partially includes in each case the data memory sections of at least two of the output variable vectors of two different neuron layers of the neuron layers.

2. The model calculation unit as recited in claim 1 , wherein the data memory section for the input variable vector assigned to at least one of the neuron layers fully includes the data memory section of the output variable vector of a preceding neuron layer.

3. The model calculation unit as recited in claim 1 , wherein the data memory section for the input variable vector assigned to at least one of the neuron layers partially includes the data memory section of the output variable vector of a neuron layer other than a preceding neuron layer.

4. The model calculation unit as recited in claim 1 , wherein the data memory sections of the at least two output variable vectors of the two different neuron layers of the neuron layers adjoin one another in an address area of the data memory area.

5. The model calculation unit as recited in claim 1 , wherein the memory for each of the neuron layers includes a configuration memory area for storing configuration parameters in a respective configuration memory section, and wherein DMA unit is configured to successively instruct the processor core to calculate a neuron layer in each case based on the configuration parameters of a respective configuration memory section and on the input variable vector defined as a result, and to store the respectively resulting output variable vector in a data memory section of the data memory area defined by the corresponding configuration parameters.

6. The model calculation unit as recited in claim 1 , wherein the processor core is configured to signal the DMA unit or to signal externally, an end of an instantaneous calculation of the neuron layer, the DMA unit starting the calculation of a next neuron layer of the neuron layers based on configuration parameters stored in an additional configuration memory section.

7. The model calculation unit as recited in claim 1 , wherein the processor core is configured to calculate an output variable for each neuron of a neuron layer of the multilayer perceptron model having a number of neurons as a function of one or multiple input variables of an input variable vector, as a function of a weighting matrix having weighting factors and of an offset value predefined for each neuron, a sum of values of the input variables weighted with a weighting factor determined by the neuron and the input variable being calculated for each neuron, and a result being transformed with an activation function in order to obtain the output variable for the neuron in question.

8. The model calculation unit as recited in claim 1 , wherein the processor core is formed in a surface area of an integrated module.

9. A control unit that includes a microprocessor at least one model calculation unit, the at least one model calculation unit for calculating a multilayer perceptron model having a plurality of neuron layers, the model calculation unit being designed in hardware and being hardwired, the model calculation unit comprising:
a processor core which is configured to calculate one or multiple output variables of an output variable vector of a neuron layer of the multilayer perceptron model having a number of neurons as a function of one or of multiple input variables of an input variable vector;
a memory which a data memory area is provided, in which each neuron layer is assigned a data memory section for storing the input variables of the input variable vector and a data memory section for storing the output variables of the output variable vector; and
a DMA unit which is configured to successively instruct the processor core to calculate a neuron layer, in each case based on input variables of the assigned input variable vector and to store the respectively resulting output variables of the output variable vector in the assigned data memory section;
wherein the data memory section for the input variable vector assigned to at least one of the neuron layers at least partially includes in each case the data memory sections of at least two of the output variable vectors of two different neuron layers of the neuron layers.

10. The control unit as recited in claim 9 , wherein the control unit is an integrated circuit.

11. A use of the control unit, comprising:
providing a control unit, the control unit including a microprocessor at least one model calculation unit, the at least one model calculation unit for calculating a multilayer perceptron model having a plurality of neuron layers, the model calculation unit being designed in hardware and being hardwired, the model calculation unit including: a processor core which is configured to calculate one or multiple output variables of an output variable vector of a neuron layer of the multilayer perceptron model having a number of neurons as a function of one or of multiple input variables of an input variable vector, a memory which a data memory area is provided, in which each neuron layer is assigned a data memory section for storing the input variables of the input variable vector and a data memory section for storing the output variables of the output variable vector, and a DMA unit which is configured to successively instruct the processor core to calculate a neuron layer, in each case based on input variables of the assigned input variable vector and to store the respectively resulting output variables of the output variable vector in the assigned data memory section, wherein the data memory section for the input variable vector assigned to at least one of the neuron layers at least partially includes in each case the data memory sections of at least two of the output variable vectors of two different neuron layers of the neuron layers;
using the control unit to control an engine system in a motor vehicle.

Assignees

• Bosch Gmbh Robert

Inventors

• Guntoro Andre
• Markert Heiner
• Schiegg Martin

Classifications

• G06N3/0442

  characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU] · CPC title

• G06N3/0499

  Feedforward networks · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title