Lithography-based pattern optimization

Patent metadata

Field	Value
Publication number	US-11449659-B2
Application number	US-202016868298-A
Country	US
Kind code	B2
Filing date	May 6, 2020
Priority date	Jun 3, 2019
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

An example is a method. An electronic representation of a design of an integrated circuit to be manufactured on a semiconductor die is obtained. The design of the integrated circuit includes layers. The electronic representation includes initial polygons. Polygon topological skeletons of the initial polygons of the target layer are generated. A space topological skeleton in a space between the polygon topological skeletons is generated. A connected network comprising network edges is generated. Each network edge is connected between a respective polygon topological skeleton and the space topological skeleton. A transformation of the polygon topological skeletons is performed, by one or more processors, based on the network edges, a spacing specification for a spacing between polygons, and respective specified widths associated with the initial polygons by perturbing the polygon topological skeletons.

First claim

What is claimed is:

1. A method comprising:
obtaining an electronic representation of a design of an integrated circuit to be manufactured on a semiconductor die, the design of the integrated circuit including layers, the electronic representation including initial polygons in a target layer of the layers;
generating polygon topological skeletons of the initial polygons of the target layer;
generating a space topological skeleton in a space between the polygon topological skeletons;
generating a connected network comprising network edges, each network edge being connected between a respective polygon topological skeleton and the space topological skeleton; and
performing, by one or more processors, a transformation of the polygon topological skeletons based on the network edges of the connected network, a spacing specification for a spacing between polygons, and respective specified widths associated with the initial polygons by perturbing the polygon topological skeletons.

2. The method of claim 1 , wherein generating the polygon topological skeletons includes generating first polygon topological skeleton (PTS) nodes connected by PTS edges based on the initial polygons of the target layer.

3. The method of claim 2 , wherein generating the polygon topological skeletons includes:
deriving second PTS nodes from connections to one or more layers that are underlying or overlying the target layer, each second PTS node having a placement constraint relating to the corresponding one or more layers; and
inserting the second PTS nodes into the polygon topological skeletons, each second PTS node being connected by a respective one or more PTS edges to another PTS node.

4. The method of claim 3 , wherein generating the polygon topological skeletons includes, after generating the first PTS nodes, inserting third PTS nodes into the polygon topological skeletons, each third PTS node being connected by a respective one or more PTS edges to another PTS node, the first PTS nodes and the third PTS nodes having no placement constraint within the target layer.

5. The method of claim 1 , wherein:
the polygon topological skeletons include PTS nodes connected by PTS edges;
the space topological skeleton includes space topological skeleton (STS) nodes connected by STS edges; and
each network edge of the connected network is connected to a respective one of the PTS nodes and a respective one of the STS nodes.

6. The method of claim 5 , wherein:
each PTS node has a specified width associated with a corresponding initial polygon of the target layer;
performing the transformation is included in performing a minimization function on a cost function, performing the minimization function on the cost function perturbs at least some of the PTS nodes when the cost function is not minimized; and
the cost function includes a sum of overlap of a respective polygon distance and a space distance projected onto each network edge, the respective polygon distance being based on the specified width of the PTS node to which the respective network edge is connected and projected onto the respective network edge from the PTS node to which the respective network edge is connected, the space distance being based on the spacing specification and projected onto the respective network edge from the STS node to which the respective network edge is connected.

7. The method of claim 1 further comprising, after performing the transformation of the polygon topological skeletons by perturbing the polygon topological skeletons, transforming the polygon topological skeletons to resulting polygons in the target layer.

8. A system comprising:
a memory storing instructions; and
one or more processors, coupled with the memory and configured to execute the instructions, wherein the instructions, when executed by the one or more processors, cause the one or more processors to:
generate polygon topological skeletons based on initial polygons of a target layer in an electronic representation of a design of an integrated circuit to be manufactured on a semiconductor die, the design of the integrated circuit including layers that include the target layer, the polygon topological skeletons including polygon topological skeleton (PTS) nodes connected by PTS edges;
generate a space topological skeleton based on a space region between the polygon topological skeletons, the space topological skeleton including space topological skeleton (STS) nodes connected by STS edges;
generate a connected-node network including network edges, each network edge being connected to a respective one PTS node and a respective one STS node; and
perform a minimization function on a cost function, performing the minimization function being configured to perturb the PTS nodes until an end condition of the minimization function is reached, the cost function being based on the network edges, a spacing specification for a spacing between polygons, and respective specified widths associated with the PTS nodes connected to the network edges.

9. The system of claim 8 , wherein the PTS nodes include first PTS nodes generated based on the initial polygons of the target layer, the first PTS nodes having no placement constraint within the target layer.

10. The system of claim 9 , wherein the PTS nodes include second PTS nodes each generated based on a connection to a layer underlying or overlying the target layer, each second PTS node having a placement constraint relating to the corresponding layer underlying or overlying the target layer.

11. The system of claim 10 , wherein the PTS nodes include third PTS nodes arbitrarily inserted into the polygon topological skeletons, the third PTS nodes having no placement constraint within the target layer.

12. The system of claim 8 , wherein each PTS node has a specified width associated with a corresponding initial polygon of the target layer.

13. The system of claim 12 , wherein the cost function includes a sum of overlap of a respective polygon distance and a space distance projected onto each network edge, the respective polygon distance being based on the specified width of the PTS node to which the respective network edge is connected and projected onto the respective network edge from the PTS node to which the respective network edge is connected, the space distance being based on the spacing specification and projected onto the respective network edge from the STS node to which the respective network edge is connected.

14. The system of claim 8 , wherein the instructions, when executed by the one or more processors, further cause the one or more processors to:
after performing minimization function, transform the polygon topological skeletons to resulting polygons in the target layer.

15. A non-transitory computer readable medium comprising stored instructions, which when executed by one or more processors, cause the one or more processors to:
generate polygon topological skeletons based on initial polygons of a target layer in an electronic representation of a design of an integrated circuit, the design of the integrated circuit including layers that include the target layer, the polygon topological skeletons including polygon topological skeleton (PTS) nodes;
generate a space topological skeleton between the polygon topological skeletons, the space topological skeleton including space topological skeleton (STS) nodes;
generate a connected-node network including network edges, each network edge being connected to a respective one PTS node and a respective one STS node; and
perform a minimization function on a cost function configured to perturb th

Assignees

• Synopsys Inc

Inventors

• Cecil Thomas

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title