General-purpose parallel computing architecture

Patent metadata

Field	Value
Publication number	US-11449452-B2
Application number	US-201715481201-A
Country	US
Kind code	B2
Filing date	Apr 6, 2017
Priority date	May 21, 2015
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

An apparatus includes multiple computing cores, where each computing core is configured to perform one or more processing operations and generate input data. The apparatus also includes multiple coprocessors associated with each computing core, where each coprocessor is configured to receive the input data from at least one of the computing cores, process the input data, and generate output data. The apparatus further includes multiple reducer circuits, where each reducer circuit is configured to receive the output data from each of the coprocessors of an associated computing core, apply one or more functions to the output data, and provide one or more results to the associated computing core. In addition, the apparatus includes multiple communication links communicatively coupling the computing cores and the coprocessors associated with the computing cores.

First claim

What is claimed is:

1. An apparatus comprising:
multiple computing cores, each computing core configured to perform one or more processing operations and generate input data;
multiple sets of coprocessors each uniquely associated with a different one of the computing cores, each coprocessor configured to receive the input data from at least one of the computing cores, process the input data, and generate output data;
multiple reducer circuits each uniquely associated with a different one of the computing cores, each reducer circuit configured to receive the output data from the coprocessors in the set of coprocessors associated with one of the computing core uniquely associated with the reducer circuit, apply one or more functions to the output data, and provide one or more results to the computing core uniquely associated with the reducer circuit; and
multiple communication links communicatively coupling the computing cores and at least some of the coprocessors.

2. The apparatus of claim 1 , wherein the communication links comprise direct connections between the computing cores and at least some of the coprocessors.

3. The apparatus of claim 1 , wherein the communication links comprise one or more direct connections between at least one of the computing cores and one or more coprocessors at a beginning of one or more chains of coprocessors.

4. The apparatus of claim 1 , wherein:
the communication links comprise a direct connection between one of the computing cores and one of the coprocessors; and
the one of the coprocessors is coupled to multiple additional ones of the coprocessors.

5. The apparatus of claim 1 , wherein at least some of the coprocessors are arranged in at least one tree.

6. The apparatus of claim 1 , wherein the communication links comprise links to a shared resource, the shared resource configured to store the input data from the computing cores and to provide the input data to the coprocessors.

7. The apparatus of claim 6 , wherein the shared resource comprises a shared memory.

8. The apparatus of claim 7 , wherein:
the shared memory comprises multiple memory locations having multiple memory addresses;
the computing cores are configured to write the input data to different memory addresses; and
the coprocessors are configured to read the input data from the different memory addresses.

9. An apparatus comprising:
multiple computing cores, each computing core configured to perform one or more processing operations and generate input data;
multiple sets of coprocessors each uniquely associated with a different one of the computing cores, each coprocessor configured to receive the input data from at least one of the computing cores, process the input data, and generate output data; and
multiple communication links communicatively coupling the computing cores and at least some of the coprocessors;
wherein a subset of the coprocessors in each set of coprocessors is also configured to collectively apply one or more functions to the output data generated by the coprocessors in that set of coprocessors, one of the coprocessors in each set of coprocessors further configured to provide one or more results to the computing core uniquely associated with that set of coprocessors.

10. The apparatus of claim 9 , wherein the communication links comprise direct connections between the computing cores and at least some of the coprocessors.

11. The apparatus of claim 9 , wherein the communication links comprise one or more direct connections between at least one of the computing cores and one or more coprocessors at a beginning of one or more chains of coprocessors.

12. The apparatus of claim 9 , wherein:
the communication links comprise a direct connection between one of the computing cores and one of the coprocessors; and
the one of the coprocessors is coupled to multiple additional ones of the coprocessors.

13. The apparatus of claim 9 , wherein at least some of the coprocessors are arranged in at least one tree.

14. The apparatus of claim 9 , wherein the communication links comprise links to a shared resource, the shared resource configured to store the input data from the computing cores and to provide the input data to the coprocessors.

15. The apparatus of claim 14 , wherein the shared resource comprises a shared memory.

16. The apparatus of claim 15 , wherein:
the shared memory comprises multiple memory locations having multiple memory addresses;
the computing cores are configured to write the input data to different memory addresses; and
the coprocessors are configured to read the input data from the different memory addresses.

17. An apparatus comprising:
N parallel computing cores, each computing core configured to perform one or more processing operations and generate input data;
N×N coprocessors, wherein each computing core is associated with N distinct parallel coprocessors, each coprocessor configured to receive the input data from at least one of the computing cores, process the input data, and generate output data;
N reducer circuits, each computing core associated with a distinct one of the reducer circuits, each reducer circuit configured to receive the output data from the N coprocessors of the computing core distinctly associated with the reducer circuit, apply one or more functions to the output data, and provide one or more results to the computing core distinctly associated with the reducer circuit; and
multiple communication links communicatively coupling the computing cores and at least some of the coprocessors.

18. The apparatus of claim 17 , wherein N is an integer having a value of at least sixteen.

19. The apparatus of claim 17 , wherein the communication links comprise links to a shared resource, the shared resource configured to store the input data from the computing cores and to provide the input data to the coprocessors.

20. The apparatus of claim 19 , wherein:
the shared resource comprises a shared memory;
the shared memory comprises multiple memory locations having multiple memory addresses;
the computing cores are configured to write the input data to different memory addresses; and
the coprocessors are configured to read the input data from the different memory addresses.

Assignees

• Goldman Sachs & Co
• Goldman Sachs & Co Llc

Inventors

• Burchard Paul
• Drepper Ulrich

Classifications

• G06N7/01

  Probabilistic graphical models, e.g. probabilistic networks · CPC title

• G06F15/8023

  Two dimensional arrays, e.g. mesh, torus · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06N20/00 Primary

  Machine learning · CPC title

• G06N3/063

  using electronic means · CPC title