Printed circuit boards with non-functional features

Patent metadata

Field	Value
Publication number	US-11445599-B2
Application number	US-202016998977-A
Country	US
Kind code	B2
Filing date	Aug 20, 2020
Priority date	Jan 29, 2019
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).

First claim

What is claimed is:

1. A printed circuit board (PCB) comprising:
a plurality of layers each including an insulator and a portion of circuitry;
a first hole that passes through the plurality of layers; and
a conductive first via that is formed in the first hole, that includes a portion of the circuitry, and that passes through one or more of the plurality of layers,
wherein each of the plurality of layers includes only one conductive first Non-Functional Features (NFFs) that physically contacts the first via, and wherein a respective interface between each first NFF and the first via does not completely laterally surround the first via, and
wherein respective centerlines of consecutive first NFFs contacting the first via extend from a center axis of the first hole at different angular positions relative to each others that are separated by at most 120 degrees.

2. The PCB of claim 1 , wherein each first NFF is integral with the first via.

3. The PCB of claim 1 , wherein in a top view each of the first NFFs form a ring sector, and wherein the respective interfaces between the first NFFs and the first via is an arc of an inner circle of the ring sector.

4. The PCB of claim 1 , further comprising:
a back drilled portion of the hole that extends from the hole and that does not include the first via.

5. The PCB of claim 1 , further comprising:
a second hole that passes through the plurality of layers; and
a conductive second via that is formed in the second hole, that includes a portion of the circuitry, and that passes through the plurality of layers,
wherein each of the plurality of layers includes only one conductive second NFF that physically contacts the second via, and wherein a respective interface between each second NFF and the second via does not completely laterally surround the second via, and
wherein respective centerlines of consecutive second NFFs contacting the second via extend from a center axis of the second hole at different angular positions relative to each others that are separated by at most 120 degrees.

6. The PCB of claim 5 , wherein the first via and the second via are a pair of differential vias.

7. The PCB of claim 6 , wherein any particular layer in the plurality of layers includes a first NFF contacting the first via in a first orientation relative to the first via, and a second NFF contacting the second via in a second orientation relative to the second via that rotated 180 degrees relative to the first orientation of the first NFF relative to the first via.

8. The PCB of claim 1 , wherein the different angular positions of consecutive first NFFs contacting the first via produces a thermal stress reduction that is more uniform relative to consecutive NFFs with the same angular positions on a via.

9. The PCB of claim 1 , wherein consecutive first NFFs contacting the first via are oriented at a predefined angle relative to each other.

10. The PCB of claim 1 , wherein an angle spanned by each of the first NFFs is between 20 degrees and 150 degrees.

11. A printed circuit board (PCB) comprising:
a printed circuit board;
a first via providing a portion of the circuitry and passing through at least a portion of the printed circuit board; and
a plurality of first Non-Functional Features (NFFs) that each extend from the first via but that each do not completely laterally surrounding the first via,
wherein only one of the plurality of first NFFs extends from the first via in each of a plurality of different layers in the circuit board, and wherein respective centerlines of consecutive first NFFs extending from a central axis of the first via are located at different angular positions relative to each others that are separated by at most 120 degrees.

12. The PCB of claim 11 , wherein in a top view, each of the plurality of first NFFs extends from the first via as a strip that runs along a circumference of the first via and that has a uniform width.

13. The PCB of claim 11 , further comprising:
a second via providing a portion of the circuitry and passing through at least a portion of the printed circuit board; and
a plurality of second NFFs that each extending from the second via but that each do not completely laterally surrounding the first via,
wherein only one of the plurality of second NFFs extends from the second via in each of a plurality of different layers in the circuit board, and wherein respective centerlines of consecutive second NFFs extending from a central axis of the second via are located at different angular positions relative to each others that are separated by at most 120 degrees.

14. The PCB of claim 13 , wherein the first via and the second via are a pair of differential vias.

15. The PCB of claim 14 , wherein any particular layer in the printed circuit board includes a first NFF contacting the first via in a first orientation relative to the first via, and a second NFF contacting the second via in a second orientation relative to the second via that rotated 180 degrees relative to the first orientation of the first NFF relative to the first via.

16. The PCB of claim 11 , wherein the different angular positions of consecutive first NFFs extending from the first via produces a thermal stress reduction that is more uniform relative to consecutive NFFs with the same angular positions on a via.

17. The PCB of claim 11 , wherein consecutive first NFFs extending from the first via are oriented at a predefined angle relative to each other.

18. The PCB of claim 11 , wherein an angle spanned by each of the plurality of first NFFs is between 20 degrees and 150 degrees.

19. A method for manufacturing the printed circuit board (PCB) of claim 11 , the method comprising:
forming a plurality of layers each of which comprises an insulator and comprises a portion of a circuitry of the printed circuit board, wherein each of one or more of the layers comprises one or more conductive features each of which comprises one or more non-functional features (NFFs); then
attaching the layers to each other to form a stack of the layers; then
forming the one or more holes through one or more of the layers, wherein each of one or more of the holes has a boundary shared with at least one NFF that does not completely laterally surround the hole; then
forming one or more conductive vias comprising a portion of the circuitry and passing through one or more of the layers, each via being formed in a corresponding one of the one or more holes, wherein the boundary of each NFF physically contacts a via formed in the hole sharing the boundary with the NFF;
wherein at least one of the vias physically contacts a plurality of corresponding NFFs that are located in different layers at different angular positions relative to the via.

20. The method of claim 19 , wherein the one or more conductive vias comprise a pair of differential vias, and the stack of layers comprises a first plurality of layers each of which comprises two NFFs each of which physically contacts a corresponding one of the differential vias.

Assignees

• Dell Products Lp

Inventors

• Chandra Umesh
• Mutnury Bhyrav M

Classifications

• H05K1/114

  Pad being close to via, but not surrounding the via · CPC title

• H05K1/116 Primary

  Lands, clearance holes or other lay-out details concerning the surrounding of a via · CPC title

• H05K1/0245 Primary

  Lay-out of balanced signal pairs, e.g. differential lines or twisted lines · CPC title

• H05K1/113

  Via provided in pad; Pad over filled via · CPC title

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title