Low power mmWave receiver architecture with spatial compression interface

Patent metadata

Field	Value
Publication number	US-11444645-B2
Application number	US-201816958813-A
Country	US
Kind code	B2
Filing date	Jan 2, 2018
Priority date	Jan 2, 2018
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

A receiver circuit associated with a communication device is disclosed. The receiver circuit comprises a digital data compression circuit configured to receive a plurality of digital receive signals derived from a plurality of analog receive signals respectively associated with the receiver circuit. The digital data compression circuit is further configured to compress the plurality of digital receive signals to form one or more compressed digital data signals based thereon, to be provided to an input output (I/O) interface associated therewith. In some embodiments, a compressed digital signal dimension associated with the one or more compressed digital data signals is less than a digital signal dimension associated with the plurality of digital receive signals.

First claim

What is claimed is:

1. A receiver circuit associated with a communication device configured to operate in a digital mode or a hybrid mode, the receiver circuit comprising:
an analog-to-digital converter (ADC) circuit configured to digitize a plurality of analog receive signals to generate plurality of digital receive signals;
a digital data compression circuit coupled to the ADC circuit and configured to, during the digital mode
receive the plurality of digital receive signals;
determine a data compression metric based on the plurality of digital receive signals; and
compress the plurality of digital receive signals based on the data compression metric to form one or more compressed digital data signals based thereon,
wherein a compressed digital signal dimension associated with the one or more compressed digital data signals is dictated by the data compression metric and is less than a digital signal dimension associated with the plurality of digital receive signals;
wherein the digital data compression circuit is selectively activated during the digital mode and is selectively deactivated during the hybrid mode; and

an analog data compression circuit coupled to the ADC circuit, configured, during the hybrid mode, to:
receive the data compression metric determined by the digital data compression circuit during the digital mode;
compress the plurality of analog receive signals based on the data compression metric to generate one or more compressed analog data signals, wherein a number of compressed analog data signals is dictated by the data compression metric;
provide the one or more compressed analog receive signals to the ADC circuit for conversion to a corresponding one or more compressed digital data signals;
wherein the analog data compression circuit is selectively activated during the hybrid mode and is selectively deactivated during the digital mode; and

an input output (I/O) interface circuit configured to receive the one or more compressed digital data signals, wherein a total number of signals received at the I/O interface circuit is less than a number of analog receive signals in the plurality of analog receive signals.

2. The receiver circuit of claim 1 , wherein the digital data compression circuit comprises a compression parameter determination circuit configured to determine the data compression metric, at least in part, based on measurements associated with the plurality of digital receive signals.

3. The receiver circuit of claim 2 , wherein the compression parameter determination circuit is further configured to adaptively change the data compression metric in real-time, based on monitoring one or more parameters associated with the plurality of digital receive signals or based on a feedback signal from a baseband processor associated therewith, or both.

4. The receiver circuit of claim 1 , wherein the digital data compression circuit further comprises a quantization circuit configured to quantize the one or more compressed digital data signals, prior to providing the one or more compressed digital data signals to the I/O interface circuit.

5. The receiver circuit of claim 1 , further comprising an analog front-end circuit configured to receive the plurality of analog receive signals from a plurality of antennas, respectively associated therewith and provide the plurality of analog receive signals to the ADC circuit.

6. The receiver circuit of claim 1 , wherein the digital signal dimension refers to a number of digital receive signals in the plurality of digital receive signals, and wherein the compressed digital signal dimension refers to a number of compressed digital data signals in the one or more compressed digital data signals.

7. A method for a receiver circuit, comprising:
during a digital mode of operation of the receiver circuit,
activating a digital data compression circuit and deactivating an analog data compression circuit;
receiving, at the digital data compression circuit, a plurality of digital receive signals respectively derived from a plurality of analog receive signals associated with the receiver circuit;
determining a data compression metric based on the plurality of digital receive signals;
compressing, at the digital data compression circuit, the plurality of digital receive signals based on the data compression metric to form one or more compressed digital data signals based thereon, wherein a compressed digital signal dimension associated with the one or more compressed digital data signals is dictated by the data compression metric and is less than a digital signal dimension associated with the plurality of digital receive signals;

during a hybrid mode of operation of the receiver circuit,
activating the analog data compression circuit and deactivating the digital data compression circuit;
receiving, at the analog data compression circuit, the data compression metric determined by the digital data compression circuit during the digital mode of operation of the receiver circuit;
compressing the plurality of analog receive signals based on the data compression metric to generate one or more compressed analog data signals, wherein a number of compressed analog data signals is dictated by the data compression metric; and
providing the one or more compressed analog receive signals to an ADC circuit for conversion to a corresponding one or more compressed digital data signals; and

receiving at an input output (I/O) interface circuit the one or more compressed digital data signals, wherein a total number of signals received at the I/O interface circuit is less than a number of analog receive signals in the plurality of analog receive signals.

8. The method of claim 7 , further comprising adaptively changing the data compression metric at the digital data compression circuit, at least in part, based on measurements associated with the plurality of digital receive signals.

9. The method of claim 8 , comprising adaptively changing the data compression metric in real-time, based on monitoring one or more parameters associated with the plurality of digital receive signals or based on a feedback signal from a baseband processor associated therewith, or both.

10. A receiver circuit associated with a communication device comprising:
analog front-end circuit configured to receive a plurality of analog receive signals from a plurality of antennas, respectively associated with the receiver circuit, wherein the plurality of analog receive signals comprises an analog signal dimension associated therewith, wherein the analog signal dimension refers to the number of analog receive signals in the plurality of analog receive signals;
an analog-to-digital converter (ADC) circuit configured to receive the plurality of analog receive signals from the analog front end circuit and digitize the plurality of analog receive signals to generate the plurality of digital receive signals;
a digital data compression circuit selectively activated during a digital mode of operation of the receiver circuit and selectively deactivated during a hybrid mode of operation of the receiver circuit, the digital data compression circuit configured to, during the digital mode,
receive a plurality of digital receive signals derived from a plurality of analog receive signals associated with the receiver circuit, wherein the plurality of digital receive signals comprises a digital signal dimension associated therewith, wherein the digital signal dimension refers to a number of digital receive signals in the plurality of digital receive signals;
determine a data compression metric based on the plurality of digital receive signals; and
compress the plurality of digital receive signals to form one

Assignees

• Apple Inc

Inventors

• Orhan Oner
• Nikopour Hosein
• Sagazio Peter
• Sheikh Farhana
• Nam Junyoung
• Talwar Shilpa

Classifications

• H03M7/30

  Compression (speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N); Expansion; Suppression of unnecessary data, e.g. redundancy reduction · CPC title

• H04B7/0413 Primary

  MIMO systems · CPC title

• H04B1/16 Primary

  Circuits · CPC title

• H03M7/70

  Type of the data to be coded, other than image and sound · CPC title