Clock phase-shifting techniques in physical layout design

Patent metadata

Field	Value
Publication number	US-11444625-B2
Application number	US-202017103585-A
Country	US
Kind code	B2
Filing date	Nov 24, 2020
Priority date	Nov 24, 2020
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

Various implementations described herein are related to a device. The device may include first circuitry that receives a clock signal and provides one or more phase-shifted pulse signals based on the clock signal. The device may include second circuitry that receives an input voltage, receives the clock signal, and provides an internal control signal based on the input voltage and the clock signal. The device may include third circuitry that receives the internal control signal, receives the one or more phase-shifted pulse signals, and provides an output clock signal based on the internal control signal and the one or more phase-shifted pulse signals.

First claim

What is claimed is:

1. A device, comprising:
first circuitry that receives a clock signal and provides one or more phase-shifted pulse signals based on the clock signal;
second circuitry that receives an input voltage, receives the clock signal, and provides an internal control signal based on the input voltage and the clock signal;
third circuitry that receives the internal control signal, receives the one or more phase-shifted pulse signals, and provides an output clock signal based on the internal control signal and the one or more phase-shifted pulse signals; and
a phase locked loop circuit that receives a reference clock from an external source, generates a phase locked loop clock signal, and then provides the phase locked loop clock signal to the first circuitry and the second circuity.

2. The device of claim 1 , wherein:
the first circuitry refers to a digital locked loop circuit that receives the clock signal as the phase locked loop clock signal,
the second circuitry refers to a droop detection circuit that receives the input voltage as a core voltage and provides the internal control signal as a digital internal control signal,
the third circuitry refers to a phase shifter circuit that provides the output clock signal as a digital output clock signal.

3. The device of claim 2 , wherein the droop detection circuit receives the core voltage from an external supply, receives the phase locked loop clock signal from the phase locked loop circuit, generates the digital internal control signal based on the core voltage and the phase locked loop clock signal, and then provides the digital internal control signal to the phase shifter circuit.

4. The device of claim 2 , wherein:
the phase shifter circuit is configured to operate as a rotating phase selector circuit for intelligent clock stretching of high performance digital circuits, and
the one or more phase-shifted pulse signals refer to multiple phase-shifted pulse signals with each phase-shifted pulse signal having a shifted phase with respect to each other phase-shifted pulse signal.

5. The device of claim 2 , further comprising:
a post scalar output circuit that receives the digital output clock signal from the phase shifter circuit, generates a scaled digital output clock signal based on the digital output clock signal, and provides the scaled digital output clock signal to an external computing device.

6. The device of claim 5 , wherein the external computing device refers to a processor for use with at least one of a central processing unit (CPU) and a graphics processing unit (GPU), and wherein the scaled digital output clock signal refers to a CPU clock signal or a GPU clock signal for the processor.

7. The device of claim 6 , wherein the device operates as flexible clocking circuitry that is configured to generate the CPU clock signal or the GPU clock signal for the CPU that allows for reduction of a voltage margin of the core voltage by automatically slowing down the CPU clock or the GPU clock when a large voltage transient occurs in the core voltage.

8. The device of claim 6 , wherein the device operates as flexible clocking circuitry that is configured to lower a clock frequency of the CPU clock or the GPU clock when a voltage droop starts to occur in the core voltage, and when current to the CPU or GPU drops, the device reduces the voltage droop in the core voltage.

9. The device of claim 6 , wherein the device operates as flexible clocking circuitry that is configured to momentarily reduce digital circuit speed of the CPU or the GPU by lowering clock frequency of the CPU clock or the GPU clock when a voltage droop occurs in the core voltage.

10. A device, comprising:
a digital locked loop that provides pulse signals with shifted phases;
a droop detector that detects a voltage droop in a core voltage signal and provides an internal control signal based on detecting the voltage droop in the core voltage signal;
a phase shifter that receives the internal control signal from the droop detector, receives the pulse signals from the digital locked loop, stretches frequency of the internal control signal via rotating phase selection of the shifted phases of the pulse signals, and provides an output clock signal based on the stretched frequency of the internal control signal, and
a phase locked loop that receives a reference clock from an external clocking source, generates a phase locked loop clock signal, and provides the phase locked loop clock signal to the digital locked loop and droop detector.

11. The device of claim 10 , wherein the pulse signals refer to multiple consecutive phase-shifted pulse signals with each phase-shifted pulse signal having a shifted phase with respect to each other phase-shifted pulse signal.

12. The device of claim 10 , wherein the droop detector receives the core voltage signal from an external supply, receives the phase locked loop clock signal from the phase locked loop, generates the internal control signal based on the core voltage signal and the phase locked loop clock signal, and provides the internal control signal to the phase shifter.

13. The device of claim 10 , wherein the digital locked loop receives the phase locked loop clock signal from the phase locked loop, generates the pulse signals with the shifted phases based on the phase locked loop clock signal, and provides the pulse signals as phase-shifted pulse signals to the phase shifter.

14. The device of claim 10 , further comprising:
a post scalar output circuit that receives the output clock signal from the phase shifter, generates a scaled output clock signal based on the output clock signal, and provides the scaled output clock signal to an external computing device.

15. A method, comprising:
generating pulse signals with shifted phases;
detecting a voltage droop in a core voltage signal;
providing an internal digital clock signal based on detecting the voltage droop in the core voltage signal;
stretching frequency of the internal digital clock signal via rotating phase selection of the shifted phases of the pulse signals;
providing an output digital clock signal based on the stretched frequency of the internal control signal;
generating a phase locked loop clock signal based on a reference clock signal; and
generating the internal digital clock signal based on the core voltage signal and the phase locked loop clock signal.

16. The method of claim 15 , wherein the pulse signals refer to multiple consecutive phase-shifted pulse signals with each phase-shifted pulse signal having a shifted phase with respect to each other phase-shifted pulse signal.

17. The method of claim 15 , further comprising:
generating the pulse signals with the shifted phases based on the phase locked loop clock signal; and
generating a scaled output digital clock signal based on the output digital clock signal for an external computing device.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Labbe Benoit
• Das Shidhartha
• Achuthan Thanusree

Classifications

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L7/0812

  and where no voltage or current controlled oscillator is used · CPC title