Wafer-scale satellite with integrated propulsion and attitude control

Patent metadata

Field	Value
Publication number	US-11444027-B2
Application number	US-202016875367-A
Country	US
Kind code	B2
Filing date	May 15, 2020
Priority date	May 15, 2019
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

A wafer-scale satellite bus and a manner of making the same include using wafer reconstruction techniques to stack functional diced circuits onto each other and bond them. The disclosed techniques allow for a variety of functions in each die, including providing, without limitation: ground-based communications, attitude and propulsion control, fuel tanks and thrusters, and power generation. The wafers are initially manufactured according to a common wafer design that provides electrical and power interconnects, then different wafers are further processed using subsystem-specific techniques. The circuits on differently-processed wafers are reconstructed into a single stack using e.g. wafer bonding. Surface components are mounted, and the circuitry is diced to form the final satellites. Mission-specific functions can be incorporated, illustratively by surface-mounting, to the bus at an appropriate stage of assembly, on-wafer circuitry or instrument packages for performing these functions.

First claim

What is claimed is:

1. A method of manufacturing a satellite, the method comprising:
forming, on wafers, a plurality of uniform bus dice, each bus die in the plurality of uniform bus dice comprising interconnects for conveying electrical signals and for powering circuitry connected thereto;
processing, on each of a plurality of the wafers, the uniform bus dice according to a respective different function in a plurality of subsystem functions that includes at least control over spatial attitude and propulsion of the satellite in a microgravity environment, wherein processing at least one such uniform bus die includes forming a cavity in the bus die and mounting unpackaged circuitry within the cavity; and
bonding the processed wafers to form the satellite in a stack so as to protect the circuitry mounted within the cavity.

2. The method according to claim 1 , wherein forming on wafers includes forming on wafers of silicon, or glass, or an organic substrate.

3. The method according to claim 1 , wherein forming the plurality of uniform bus dice comprises:
forming, in each of the wafers, through-wafer vias;
forming, in the through-wafer vias, the interconnects for conveying electrical signals; and
forming, on a top surface and a bottom surface of each of the wafers, the interconnects for powering circuitry connected thereto.

4. The method according to claim 1 , wherein processing each of the wafers includes processing the wafer to provide, by the wafer: a communication function, or a fuel storage function, or a propulsive function, or an attitude control function, or a power generation function, or a satellite control function, or any combination thereof.

5. The method according to claim 1 , wherein processing each of the wafers includes forming a through-wafer via, or forming a cavity in the wafer, or surface-mounting circuitry diced from the wafer or from a different wafer, or any combination thereof.

6. The method according to claim 1 , further comprising processing a given wafer according to a mission-specific subsystem function, wherein bonding the stack of the processed wafers includes bonding the stack including the given wafer.

7. The method according to claim 6 , wherein bonding the stack including the given wafer comprises bonding the stack having, in order: a processed wafer having a communication function; the given wafer; a processed wafer having a propulsive function; and a processed wafer having a power generation function.

8. The method according to claim 1 , wherein processing the at least one uniform bus die further includes backfilling a cavity in its wafer, or planarizing the bus die for stacking, or both backfilling and planarizing.

9. The method according to claim 1 , wherein the bonded stack of processed wafers comprises a plurality of satellites, the method further comprising dicing the bonded stack to separate the satellites from each other.

10. A satellite comprising:
a plurality of wafers, each wafer comprising a uniform bus die having interconnects for conveying electrical signals and for powering circuitry connected thereto, each wafer further comprising the circuitry connected thereto according to a respective different function in a plurality of subsystem functions that includes at least control over spatial attitude and propulsion of the satellite in a microgravity environment;
wherein at least one wafer in the plurality of wafers comprises a cavity into which an unpackaged circuit has been mounted; and
wherein the plurality of wafers were bonded to form the satellite in a stacked configuration so as to protect the circuit within the cavity.

11. The satellite according to claim 10 , wherein at least one of the plurality of wafers comprises silicon, or glass, or an organic substrate.

12. The satellite according to claim 10 , wherein each uniform bus die comprises one or through-wafer vias having interconnects for conveying the electrical signals.

13. The satellite according to claim 10 , wherein each uniform bus die comprises, on a top surface and a bottom surface of its wafer, the interconnects for powering circuitry connected thereto.

14. The satellite according to claim 10 , wherein the circuitry mounted to each wafer comprises circuitry for providing: a communication function, or a fuel storage function, or a propulsive function, or an attitude control function, or a power generation function, or a satellite control function, or any combination thereof.

15. The satellite according to claim 10 , wherein each of the wafers further includes, according to the respective function of the circuitry connected thereto: a through-wafer via, or a cavity in the wafer, or surface-mounting circuitry diced from the wafer or from a different wafer, or any combination thereof.

16. The satellite according to claim 10 , wherein a given wafer in the plurality of wafers has a mission-specific subsystem function.

17. The satellite according to claim 16 , wherein the stacked configuration has, in order: a processed wafer having a communication function; the given wafer having the mission-specific subsystem function; a processed wafer having a propulsive function; and a processed wafer having a power generation function.

18. The satellite according to claim 10 , further comprising backfill in the cavity.

19. The satellite according to claim 10 , wherein each uniform bus die has been planarized for stacking.

20. A plurality of satellites according to claim 10 , in orbit around the Earth and acting separately, or as a cluster, or as a constellation.

Assignees

• Massachusetts Inst Technology

Inventors

• Rothschild Mordechai
• Kaushik Sumanth
• Smith Melissa A
• Racz Livia
• Burianek Dennis

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/427 Primary

  Power or ground buses · CPC title

• B64G1/244

  Spacecraft control systems · CPC title

• B64G1/10

  Artificial satellites; Systems of such satellites; Interplanetary vehicles (space shuttles B64G1/14) · CPC title