Packaged electronic device with split die pad in robust package substrate

Patent metadata

Field	Value
Publication number	US-11444012-B2
Application number	US-202016831503-A
Country	US
Kind code	B2
Filing date	Mar 26, 2020
Priority date	Mar 26, 2020
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

In a described example, an apparatus includes a package substrate with a split die pad having a slot between a die mount portion and a wire bonding portion; a first end of the wire bonding portion coupled to the die mount portion at one end of the slot; a second end of the wire bonding portion coupled to a first lead on the package substrate. At least one semiconductor die is mounted on the die mount portion; a first end of a first wire bond is bonded to a first bond pad on the at least one semiconductor die; a second end of the first wire bond is bonded to the wire bonding portion; and mold compound covers the at least one semiconductor die, the die mount portion, the wire bonding portion, and fills the slot.

First claim

What is claimed is:

1. An apparatus, comprising:
a package substrate with a split die pad having a slot between a die mount portion and a wire bonding portion with smaller area than the die mount portion;
a first end of the wire bonding portion directly attached and physically connected to the die mount portion at one end of the slot;
a second end of the wire bonding portion coupled to a first lead on the package substrate;
at least one semiconductor die mounted on the die mount portion;
a first end of a first wire bond bonded to a first bond pad on the at least one semiconductor die;
a second end of the first wire bond bonded to the wire bonding portion;
a first end of a second wire bond bonded to a second bond pad on the at least one semiconductor die;
a second end of the second wire bond bonded to a signal lead on the package substrate;
mold compound covering the at least one semiconductor die, the die mount portion, the wire bonding portion, and filling the slot; and
the mold compound covering at least a portion of the signal lead and at least a portion of the first lead.

2. The apparatus of claim 1 , the package substrate further comprising a damping tab coupled between the die mount portion and the wire bonding portion.

3. The apparatus of claim 2 , wherein a shorting bar couples the damping tab to the wire bonding portion.

4. The apparatus of claim 1 , wherein the package substrate is a lead frame.

5. The apparatus of claim 1 , wherein a width of the slot is at least 0.100 millimeters.

6. The apparatus of claim 1 , further comprising at least a second semiconductor die mounted on the die mount portion.

7. The apparatus of claim 1 , wherein the split die pad comprises a first split die pad and further comprising a second split die pad having a second die mount portion and a second wire bonding portion spaced from the second die mount portion by a second slot, and at least a second semiconductor die mounted on the second die mount portion.

8. The apparatus of claim 1 , wherein more than one semiconductor die is mounted on the die mount portion and the apparatus forms a semiconductor package that is a multichip module (MCM).

9. The apparatus of claim 1 , wherein the apparatus forms a semiconductor package that is one selected from a group consisting essentially of: a small outline integrated circuit (SOIC) package, a dual inline package (DIP), a quad. flat package (QFP), and a quad. flat no lead (QFN) package.

10. A method, comprising:
mounting at least one semiconductor die on a package substrate having at least one split die pad that comprises a slot separating a die mount portion from a wire bonding portion, the wire bonding portion directly attached and physically connected to the die mount portion at a first end of the slot;
coupling a first lead of the package substrate to the wire bonding portion at a second end of the slot opposite the first end of the slot;
forming a first wire bond between a first bond pad on the at least one semiconductor die and the wire bonding portion;
forming a second wire bond between a second bond pad on the at least one semiconductor die and a signal lead on the package substrate;
covering the at least one semiconductor die, the wire bonding portion, the die mount portion, the first and second wire bonds, and at least a portion of the signal lead and at least a portion of the first lead with mold compound, leaving a portion of the signal lead and the first lead not covered with mold compound; and
removing an external frame from the package substrate to form a packaged semiconductor device.

11. The method of claim 10 , further comprising:
forming at least one damping tab on the package substrate with a first side attached to the die mount portion, a second side attached to the external frame on the package substrate, with a third side adjacent to and electrically isolated from a signal lead, and with a fourth side adjacent to the first lead;
connecting the damping tab to the first lead with a shorting bar; and
removing the external frame from the damping tab after covering the semiconductor die with mold compound.

12. The method of claim 10 , wherein the slot is at least 0.100 mm wide.

13. The method of claim 10 , wherein:
the package substrate further comprises a package substrate strip with multiple individual package substrates coupled together with saw streets made of package substrate material; and
singulating individual package substrates after covering the semiconductor dies with mold compound by cutting through the saw streets.

14. The method of claim 10 , wherein the package substrate is a lead frame.

15. The method of claim 10 , wherein the package is one selected from a group consisting essentially of: a small outline integrated circuit (SOIC) package, a dual inline package (DIP), a quad. flat package (QFP), and a quad. flat no lead (QFN) package.

16. The method of claim 10 , and further comprising:
mounting at least a second semiconductor die on the die mount portion; and forming a packaged multi-chip module.

17. The method of claim 10 , further comprising:
mounting at least one second semiconductor die on a second die mount portion spaced from a second wire bonding portion by a second slot in the package substrate, a first end of the second wire bonding portion attached to the second die mount portion at one end of the second slot;
attaching a second end of the second wire bonding portion to a second lead of the package substrate;
forming a third wire bond between a third bond pad on the at least one second semiconductor die and the second wire bonding portion;
the signal lead forming a first signal lead, and forming a fourth wire bond between a fourth bond pad on the at least one second semiconductor die and a second signal lead;
filling the second slot with mold compound and covering the at least one second semiconductor die, the second die mount portion, the second wire bonding portion, and the third and fourth wire bonds with the mold compound; and
leaving a portion of the second signal lead and the second lead not covered with mold compound.

18. The method of claim 17 , wherein the package substrate comprises part of a package substrate strip with multiple multichip module package substrates coupled together by saw streets made of package substrate material;
singulating multichip module package substrates one from another by cutting through the saw streets after the mold compound covering step; and
forming individual multi-chip module packages.

19. A packaged electronic device, comprising:
a package substrate with at least one split die pad including a slot between a die mount portion and a wire bonding portion having smaller area than the die mount portion;
a first end of the wire bonding portion directly attached and physically connected to the die mount portion at one end of the slot;
a second end of the wire bonding portion coupled to a first lead on the package substrate;
at least one semiconductor die mounted on the die mount portion;
a first end of a first wire bond bonded to a first bond pad on the at least one semiconductor die;
a second end of the first wire bond bonded to the wire bonding portion;
a first end of a second wire bond bonded to a second bond pad on the at least one semiconductor die;
a second end of the second wire bond bonded to a signal lead on the package substrate;
mold compound covering the at least one semiconductor die, the die mount portion, the wire bonding portion, and filling the slot; and
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Assignees

• Texas Instruments Inc

Inventors

• Chien Yuh-Harng
• Ko Chang-Yen
• Ho Chih-Chien

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W74/016

  using moulds · CPC title

• H10W74/014

  using batch processing · CPC title