Display device having gate driver

Patent metadata

Field	Value
Publication number	US-11443674-B2
Application number	US-202117465731-A
Country	US
Kind code	B2
Filing date	Sep 2, 2021
Priority date	Sep 18, 2020
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

A display device having a gate driver, which may reduce a leakage current of a TFT and power consumption, is disclosed. Each stage of the gate driver comprises an output portion including a pull-up transistor outputting a corresponding clock of a plurality of clocks as a gate signal in response to control of a Q node, and a pull-down transistor outputting a first gate-off voltage as an off-voltage of a gate signal in response to control of a QB node; a controller charging and discharging the Q node and charging and discharging the QB node to be in an opposite state of the Q node; and a back bias circuit having a back bias node capacitance-coupled with the Q node and generating a second gate-off voltage lower than the first gate-off voltage to apply the second gate-off voltage to the back bias node for an off-period of the Q node, wherein the back bias circuit may apply the back gate bias voltage to light shielding layers of some transistors, which are turned off for the off-period of the Q node, among transistors constituting the output portion and the controller, through the back bias node, thereby reducing or minimizing a leakage current of the corresponding transistors.

First claim

The invention claimed is:

1. A display device comprising:
a display panel; and
a gate driver embedded in the display panel, the gate driver including a plurality of stages respectively driving a plurality of gate lines, each stage of the plurality including:
an output portion including a pull-up transistor pulled-up by control of a Q node, outputting an input clock of a plurality of clocks to an output terminal, and a pull-down transistor pulled-down by control of a QB node, outputting a first gate-off voltage to the output terminal;
a controller charging and discharging the Q node and charging and discharging the QB node to be in an opposite state as the Q node; and
a back bias circuit having a back bias node capacitance-coupled with the Q node and generating a second gate-off voltage lower than the first gate-off voltage to apply the second gate-off voltage to the back bias node for an off-period of the Q node by the controller,

wherein the back bias circuit applies the second gate-off voltage to light shielding layers of some transistors, which are turned off for the off-period of the Q node, among transistors constituting the output portion and the controller, through the back bias node.

2. The display device of claim 1 , wherein the back bias circuit includes:
a capacitor coupled between the Q node and the back bias node; and
a bias transistor resetting the back bias node to the second gate-off voltage for a vertical blank period of each frame by control of a stabilization signal and then floating the back bias node for an active period of each frame, and
wherein a voltage of the floated back bias node is varied depending on an operation of the Q node for the active period.

3. The display device of claim 2 , wherein the voltage of the back bias node ascends and descends along the Q node for an on-period of the Q node, and the back bias node maintains the second gate-off voltage for the off-period of the Q node.

4. The display device of claim 2 , wherein:
the bias transistor includes a first gate electrode spaced from a semiconductor layer by a gate insulating film interposed therebetween,
a light shielding layer of the bias transistor is used as a second gate electrode facing the first gate electrode and spaced from the semiconductor layer by a buffer film interposed therebetween,
the light shielding layer of the bias transistor is supplied with the stabilization signal, and
the first gate electrode is of the bias transistor floated or coupled with a source electrode of the bias transistor.

5. The display device of claim 1 , wherein the back bias node is coupled with a light shielding layer of the pull-up transistor and a light shielding layer of a QB discharging transistor discharging the QB node in response to the control of the Q node in the controller.

6. The display device of claim 5 , wherein the output portion further includes a second pull-up transistor outputting the input clock to a carry terminal in response to the control of the Q node and a second pull-down transistor outputting the first gate-off voltage to the carry terminal in response to the control of the QB node, and the back bias node is also coupled to a light shielding layer of the second pull-up transistor.

7. The display device of claim 1 , wherein the controller includes:
a first charging portion including a Q charging transistor precharging the Q node with a set signal, which is any one of a start signal and an output of a preceding stage;
a second charging portion including a QB charging transistor charging the QB node with a high potential voltage;
a first discharging portion including a Q discharging transistor discharging the Q node with the first gate-off voltage by the control of the QB node; and
a second discharging portion including a QB discharging transistor discharging the QB node with the first gate-off voltage by the control of the Q node, and
the back bias node applies the second gate-off voltage lower than the source voltage of the corresponding transistor to light shielding layers of the pull-up transistor and the QB discharging transistor for the off-period of the Q node.

8. The display device of claim 7 , wherein, each stage further comprises a stabilization portion including:
a first stabilization transistor resetting the Q node to the gate-off voltage in response to the stabilization signal for a vertical blank period of each frame;
a second stabilization transistor resetting the QB node to the gate-off voltage in response to the stabilization signal for a vertical blank period of each frame; and
a third stabilization transistor resetting the output terminal to the gate-off voltage in response to the stabilization signal for a vertical blank period of each frame.

9. The display device of claim 7 , wherein the first discharging portion further includes:
a second Q discharging transistor discharging the Q node with the first gate-off voltage in response to a reset signal and an output of a subsequent stage; and
a discharging transistor discharging the output terminal with the first gate-off voltage in response to the reset signal and the output of the subsequent stage,
the second discharging portion further includes a second QB discharging transistor discharging the QB node with the first gate-off voltage in response to the set signal,
the output portion further includes a second pull-up transistor outputting the input clock to a carry terminal in response to the control of the Q node and a second pull-down transistor outputting the first gate-off voltage to the carry terminal in response to the control of the QB node, and
the back bias node also applies the second gate-off voltage to a light shielding layer of the second pull-up transistor for the off-period of the Q node.

10. The display device of claim 7 , wherein the first discharging portion further includes an offset transistor generating an offset voltage of a high potential voltage and outputting the generated offset voltage to an offset node for the on-period of the Q node in response to the control of the Q node, each of the Q charging transistor, the QB charging transistor, the first Q discharging transistor and the second Q discharging transistor includes a pair of serial transistors, and the offset node is coupled with an intermediate node between the pair of Q charging transistors and an intermediate node between the pair of first Q discharging transistors.

11. The display device of claim 10 , wherein, each stage further comprises a stabilization portion including:
a first stabilization transistor resetting the Q node to the gate-off voltage in response to the stabilization signal for the vertical blank period;
a second stabilization transistor resetting the QB node to the gate-off voltage in response to the stabilization signal for the vertical blank period;
a third stabilization transistor resetting the output terminal to the gate-off voltage in response to the stabilization signal for the vertical blank period; and
a fourth stabilization transistor resetting the carry terminal to the gate-off voltage in response to the stabilization signal for the vertical blank period, and
the first stabilization transistor includes a pair of first stabilization transistors serially coupled to each other, and the offset node is coupled with an intermediate node between the pair of first stabilization transistors.

12. The display device of claim 1 , wherein each of the other transistors except the transistors coupled with the back bias circuit among the transistors constituting the output portion and the controller includes a corresponding light shielding layer facing a corresponding gate el

Assignees

• Lg Display Co Ltd

Inventors

• Hong Yewon
• Moon Taewoong
• Bae Junhyeon
• Kim Yeonkyung
• Shin Yeonwoo

Classifications

• G09G3/3674

  Details of drivers for scan electrodes · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2320/0214

  with crosstalk due to leakage current of pixel switch in active matrix panels · CPC title