Data bus duty cycle distortion compensation

Patent metadata

Field	Value
Publication number	US-11442877-B2
Application number	US-202016949510-A
Country	US
Kind code	B2
Filing date	Oct 30, 2020
Priority date	Oct 30, 2020
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

First claim

What is claimed is:

1. An electrical circuit device comprising:
a signal bus comprising a plurality of parallel signal paths; and
a calibration circuit, operatively coupled with the signal bus, the calibration circuit comprising:
a multiple inputs integrator circuit coupled to the plurality of parallel signal paths, the multiple inputs integrator circuit to determine an average of a plurality of duty cycles for a plurality of signals transferred via the plurality of parallel signal paths;
a comparator circuit coupled to the multiple inputs integrator circuit, the comparator circuit to compare the average of the plurality of duty cycles for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result;
a control system coupled to comparator circuit, the control system to adjust, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles; and
a decoder circuit coupled to the control system, the decoder circuit to calibrate the plurality of duty cycles of the plurality of signals using the adjusted trim value.

2. The electrical circuit device of claim 1 , wherein the multiple inputs integrator circuit comprises a plurality of passive low pass filters coupled to the plurality of parallel signal paths, the plurality of passive low pass filters to obtain a plurality of direct current (DC) level representations of the plurality of duty cycles of the plurality of signals, and wherein an output of the multiple inputs integrator circuit comprises a DC level representation for the plurality of DC level representations.

3. The electrical circuit device of claim 2 , wherein the comparator circuit is to convert the DC level representation into a representative digital signal representation, and wherein to compare the average of the plurality of duty cycles for the plurality of signals transferred via the plurality of parallel signal paths to the reference value, the comparator circuit is to compare the DC level representation to the reference value.

4. The electrical circuit device of claim 1 , wherein the reference value comprises one half of a voltage supply level.

5. The electrical circuit device of claim 1 , wherein the decoder circuit is to convert the trim value into one or more biasing voltages and/or biasing currents and apply the one or more biasing voltages and/or biasing currents to the plurality of signals transferred via the plurality of parallel signal paths to calibrate the plurality of duty cycles.

6. The electrical circuit device of claim 1 , further comprising:
a memory array, wherein the signal bus comprising the plurality of parallel signal paths is coupled to the memory array.

7. The electrical circuit device of claim 1 , wherein the distortion in the plurality of duty cycles is based at least in part on processing variations in components that form the plurality of parallel signal paths.

8. An electrical circuit device comprising:
a signal bus comprising a plurality of parallel signal paths; and
a calibration circuit, operatively coupled with the signal bus, to perform operations comprising:
determining an average duty cycle of a plurality of duty cycles for a plurality of signals transferred via the plurality of parallel signal paths;
comparing the average of the plurality of duty cycles for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result;
adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles; and
calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

9. The electrical circuit device of claim 8 , wherein the calibration circuit is to perform further operations comprising:
obtaining, using a plurality of passive low pass filters, a plurality of direct current (DC) level representations of the plurality of duty cycles of the plurality of signals;
determining a DC level representation for the plurality of DC level representations; and
converting, using a comparator, the DC level representation into a representative digital signal representation.

10. The electrical circuit device of claim 9 , wherein comparing the average of the plurality of duty cycles for the plurality of signals transferred via the plurality of parallel signal paths to the reference value comprises comparing, using the comparator, the DC level representation to the reference value.

11. The electrical circuit device of claim 8 , wherein the reference value comprises one half of a voltage supply level.

12. The electrical circuit device of claim 8 , wherein the calibration circuit is to perform further operations comprising:
converting the trim value into one or more biasing voltages and/or biasing currents; and
calibrating the plurality of duty cycles by applying the one or more biasing voltages and/or biasing currents to the plurality of signals transferred via the plurality of parallel signal paths.

13. The electrical circuit device of claim 8 , further comprising:
a memory array, wherein the signal bus comprising the plurality of parallel signal paths is coupled to the memory array.

14. The electrical circuit device of claim 8 , wherein the distortion in the plurality of duty cycles is based at least in part on processing variations in components that form the plurality of parallel signal paths.

15. A method comprising:
determining an average duty cycle for a plurality of signals transferred via a plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles;
comparing the average duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result;
adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles; and
calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

16. The method of claim 15 , further comprising:
obtaining, using a plurality of passive low pass filters, a plurality of direct current (DC) level representations of the plurality of duty cycles of the plurality of signals;
determining a DC level representation for the plurality of DC level representations; and
converting, using a comparator, the DC level representation into a representative digital signal representation.

17. The method of claim 16 , wherein comparing the average duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to the reference value comprises comparing, using the comparator, the DC level representation to the reference value.

18. The method of claim 15 , wherein the reference value comprises one half of a voltage supply level.

19. The method of claim 15 , further comprising:
converting the trim value into one or more biasing voltages and/or biasing currents; and
calibrating the plurality of duty cycles by applying the one or more biasing voltages and/or biasing currents to the plurality of signals transferred via the plurality of parallel signal paths.

20. The method of claim 15 , wherein the distortion in the plurality of duty cycles is bas

Assignees

• Micron Technology Inc

Inventors

• Wang Guan
• Ghalam Ali Feiz Zarrin
• Chen Chin-Yu
• Kim Jongin

Classifications

• G11C16/32

  Timing circuits · CPC title

• G11C29/12005

  comprising voltage or current generators · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title