Apparatus and method for using an error correction code in a memory system

Patent metadata

Field	Value
Publication number	US-11442811-B1
Application number	US-202117378176-A
Country	US
Kind code	B1
Filing date	Jul 16, 2021
Priority date	Feb 24, 2021
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

Error correction code apparatuses and memory systems are disclosed. The apparatus may include an encoder configured to generate a first result by multiplying bits of the data by a first matrix, divides parity bits into a first parity group obtained by multiplying the first result by a second matrix and a second parity group obtained by an exclusive OR operation of the first result and the first parity group, based on a plurality of polynomials determined based on the second matrix, and multiply the first result and the second matrix to generate one or more first parity bits in the first parity group, perform an exclusive OR operation on the first result and the first parity group to generate one or more second parity bits in the second parity group, and generate a codeword having the bits of the data bits and the parity bits.

First claim

What is claimed is:

1. An error correction code apparatus, comprising:
a data input node configured to receive data to be encoded; and
an encoder in communication with the data input node and configured to:
generate a first result by multiplying bits of the data by a first matrix;
divide parity bits into a first parity group and a second parity group based on a plurality of polynomials determined by a second matrix;
multiply the first result and the second matrix to generate one or more first parity bits in the first parity group;
perform an exclusive OR operation on the first result and the one or more first parity bits included in the first parity group to generate one or more second parity bits in the second parity group; and
generate a codeword having the bits of the data bits and the first and second parity bits.

2. The error correction code apparatus according to claim 1 , wherein the encoder is configured to change a calculation sequence for generating the one or more first parity bits and the one more second parity bits to reduce a number of first parity bits included in the first parity group.

3. The error correction code apparatus according to claim 1 , wherein the encoder is configured to use one or more first or second parity bits that have been calculated in the first parity group or the second parity group to perform a subsequent exclusive OR operation, based on a calculation sequence, for generating another second parity bit.

4. The error correction code apparatus according to claim 1 , wherein the encoder comprises:
a first calculator configured to multiply the bits of the data by the first matrix to output the first result;
a first selector configured to divide the parity bits into the first parity group and the second parity group;
a second calculator configured to multiply the first result by the second matrix to determine the one or more first parity bits included in the first parity group;
a second selector configured to selectively transfer an output of the second calculator for the exclusive OR operation;
determination circuitry configured to sequentially group the number of parity bits and feedback at least one parity bit for the exclusive OR operation; and
a third calculator configured to perform the exclusive OR operation on the first result and the first and second parity bits outputted from the second selector and the determination circuitry to obtain the one or more second parity bits included in the second parity group.

5. The error correction code apparatus according to claim 1 , wherein the first matrix includes: a number of rows that represents the number of the bits of data; and a number of columns that represents the number of parity bits, and the second matrix includes: a number of rows that represents the first number of parity bits; and a number of columns that represents the first number of parity bits.

6. The error correction code apparatus according to claim 1 , wherein each of the plurality of polynomials determined by multiplication of the first result and the second matrix comprises a mathematical relationship between the first result and at least part of the parity bits.

7. A memory system, comprising:
a memory device comprising a plurality of non-volatile memory cells; and
a controller in communication with the memory device and configured to store a codeword in the plurality of non-volatile memory cells or read the codeword from the plurality of non-volatile memory cells, and
wherein the controller is configured to:
multiply one or more data bits by a first matrix to generate a first result;
obtain a first parity group of parity bits by multiplying the first result by a second matrix and a second parity group of parity bits by an exclusive OR operation on the first result and the first parity group of parity bits, based on a plurality of polynomials determined based on the second matrix; and
combine the one or more data bits and the first and second parity groups of parity bits to generate the codeword.

8. The memory system according to claim 7 , wherein a length of the codeword is determined based on a length of the one or more bits programmed or read at each program operation or read operation.

9. The memory system according to claim 7 , wherein the controller is configured to change a calculation sequence for generating the one or more first parity bits in the first parity group and the one more second parity bits in the second parity group to reduce a number of first parity bits included in the first parity group.

10. The memory system according to claim 7 , wherein the controller is configured to use one or more first or second parity bits that have been calculated in the first parity group or the second parity group to perform a subsequent exclusive OR operation, based on a calculation sequence, for generating another second parity bit.

11. The memory system according to claim 7 , wherein the controller comprises:
a first calculator configured to multiply the one or more data bits by the first matrix to output the first result;
a first selector configured to divide the parity bits into the first parity group and the second parity group;
a second calculator configured to multiply the first result by the second matrix to determine the one or more first parity bits included in the first parity group;
a second selector configured to selectively transfer an output of the second calculator for the exclusive OR operation;
determination circuitry configured to sequentially group the first and second parity bits included in the first and second parity groups and feedback at least one parity bit for the exclusive OR operation; and
a third calculator configured to perform the exclusive OR operation on the first result and the first and second parity bits outputted from the second selector and the determination circuitry to obtain the one or more second parity bits included in the second parity group.

12. The memory system according to claim 7 , wherein the one or more data bits include a first number of data bits and the parity bits include a second number of parity bits, and wherein the first matrix includes: a number of columns that represents the number of parity bits; and a number of rows that represents the first number of data bits, and the second matrix includes: a number of rows that represents the second number of parity bits; and a number of columns that represents the second number of parity bits.

13. The memory system according to claim 7 , wherein each of the plurality of polynomials determined by multiplication of the first result and the second matrix comprises a mathematical relationship between the first result and at least part of the parity bits.

14. The memory system according to claim 7 , wherein the controller is configured to detect and correct an error in the codeword upon receipt of the codeword from the memory device.

15. A method for operating a memory system, comprising:
checking one or more data bits and a program command input from an external device;
multiplying the one or more data bits by a first matrix to generate a first result;
dividing parity bits into a first parity group of parity bits obtained by multiplying the first result by a second matrix and a second parity group of parity bits obtained by an exclusive OR operation on the first result and the first parity group of parity bits, based on a plurality of polynomials determined by the second matrix;
combining the one or more data bits and the first and second parity groups of parity bits to generate a codeword; and
writing the generated codeword into the

Assignees

• Sk Hynix Inc

Inventors

• Chung Bi Woong
• Lee Jung Hwan
• Huh Se Yeong
• Koo In Jae

Classifications

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/1032 Primary

  Simple parity · CPC title

• H03M13/6505

  Memory efficient implementations · CPC title

• H03M13/1148

  Structural properties of the code parity-check or generator matrix · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title