Two-dimensional array of CMOS control elements

Patent metadata

Field	Value
Publication number	US-11440052-B2
Application number	US-201916395045-A
Country	US
Kind code	B2
Filing date	Apr 25, 2019
Priority date	May 4, 2016
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

An electronic device includes a plurality of CMOS control elements arranged in a two-dimensional array and a plurality of MEMS devices. Each CMOS control element of the plurality of CMOS control elements includes at least one of a low voltage semiconductor device, a high voltage PMOS semiconductor device, and a high voltage NMOS semiconductor device. Each MEMS device of the plurality of MEMS devices is associated with a CMOS control element of the plurality of CMOS control elements. The plurality of CMOS control elements are arranged in the two-dimensional array such that low voltage semiconductor devices are only adjacent to other low voltage semiconductor devices, high voltage PMOS semiconductor devices are only adjacent to other high voltage PMOS semiconductor devices, and high voltage NMOS semiconductor devices are only adjacent to other high voltage NMOS semiconductor devices.

First claim

What is claimed is:

1. An electronic device comprising:
a plurality of CMOS control elements arranged in a two-dimensional array, each CMOS control element of the plurality of CMOS control elements comprising at least one of a low voltage semiconductor device, a high voltage PMOS semiconductor device, and a high voltage NMOS semiconductor device; and
a plurality of MEMS devices, each MEMS device of the plurality of MEMS devices associated with a CMOS control element of the plurality of CMOS control elements;
wherein the plurality of CMOS control elements are arranged in the two-dimensional array such that low voltage semiconductor devices are only adjacent to other low voltage semiconductor devices, high voltage PMOS semiconductor devices are only adjacent to other high voltage PMOS semiconductor devices, and high voltage NMOS semiconductor devices are only adjacent to other high voltage NMOS semiconductor devices.

2. The electronic device of claim 1 , wherein the MEMS devices are ultrasonic transducers.

3. The electronic device of claim 2 , wherein the ultrasonic transducers are Piezoelectric Micromachined Ultrasonic Transducer (PMUT) devices.

4. The electronic device of claim 1 further comprising:
an interconnect layer disposed between the plurality of CMOS control elements and the plurality of MEMS devices, the interconnect layer comprising electrical connections for electrically coupling each MEMS to a low voltage semiconductor device, a high voltage PMOS semiconductor device, and a high voltage NMOS semiconductor device.

5. The electronic device of claim 4 , wherein each MEMS device is electrically coupled to a low voltage semiconductor device through a capacitor.

6. The electronic device of claim 1 , wherein the low voltage semiconductor device comprises at least one of a low voltage NMOS semiconductor device and a low voltage PMOS semiconductor device.

7. The electronic device of claim 1 , wherein each CMOS control element of the plurality of CMOS control elements comprises two semiconductor devices, the plurality of CMOS control elements comprising:
a first subset of CMOS control elements, each CMOS control element of the first subset of CMOS control elements comprising a high voltage NMOS semiconductor device and a low voltage semiconductor device; and
a second subset of CMOS control elements, each CMOS control element of the second subset of CMOS control elements comprising a high voltage PMOS semiconductor device and a low voltage semiconductor device.

8. The electronic device of claim 7 , wherein the low voltage semiconductor device comprises a low voltage NMOS semiconductor device and a low voltage PMOS semiconductor device.

9. The electronic device of claim 1 , wherein each CMOS control element of the plurality of CMOS control elements comprises one semiconductor device, the plurality of CMOS control elements comprising:
a first subset of CMOS control elements, each CMOS control element of the first subset of CMOS control elements comprising a high voltage NMOS semiconductor device;
a second subset of CMOS control elements, each CMOS control element of the second subset of CMOS control elements comprising a high voltage PMOS semiconductor device; and
a third subset of CMOS control elements, each CMOS control element of the third subset of CMOS control elements comprising a low voltage semiconductor device.

10. The electronic device of claim 9 , wherein the low voltage semiconductor device comprises a low voltage NMOS semiconductor device and a low voltage PMOS semiconductor device.

11. The electronic device of claim 1 , wherein each CMOS control element of the plurality of CMOS control elements comprises three semiconductor devices, the plurality of CMOS control elements comprising a low voltage semiconductor device, a high voltage PMOS semiconductor device, and a high voltage NMOS semiconductor device.

12. The electronic device of claim 11 , wherein the low voltage semiconductor device comprises a low voltage NMOS semiconductor device and a low voltage PMOS semiconductor device.

13. An electronic device comprising:
a plurality of CMOS control elements arranged in a two-dimensional array, each CMOS control element of the plurality of CMOS control elements comprising at least one of a PMOS semiconductor device and an NMOS semiconductor device; and
a plurality of MEMS devices, each MEMS device of the plurality of MEMS devices associated with a CMOS control element of the plurality of CMOS control elements;
wherein the plurality of CMOS control elements are arranged in the two-dimensional array such that NMOS semiconductor devices are only adjacent to other NMOS semiconductor devices, and PMOS semiconductor devices are only adjacent to other PMOS semiconductor devices.

14. The electronic device of claim 13 , wherein the MEMS devices are ultrasonic transducers.

15. The electronic device of claim 14 , wherein the ultrasonic transducers are Piezoelectric Micromachined Ultrasonic Transducer (PMUT) devices.

16. The electronic device of claim 13 further comprising:
an interconnect layer disposed between the plurality of CMOS control elements and the plurality of MEMS devices, the interconnect layer comprising electrical connections for electrically coupling each MEMS to at least PMOS semiconductor device and at least one NMOS semiconductor device.

17. The electronic device of claim 13 , wherein the PMOS semiconductor device comprises a low voltage PMOS semiconductor device and a high voltage PMOS semiconductor device and the NMOS semiconductor device comprises a low voltage NMOS semiconductor device and a high voltage NMOS semiconductor device.

18. The electronic device of claim 17 , wherein each MEMS device is electrically coupled to a low voltage NMOS semiconductor device through a first capacitor and electrically coupled to a low voltage PMOS semiconductor device through a second capacitor.

19. The electronic device of claim 13 , wherein each CMOS control element of the plurality of CMOS control elements comprises two semiconductor devices, the plurality of CMOS control elements comprising:
a first subset of CMOS control elements, each CMOS control element of the first subset of CMOS control elements comprising a high voltage NMOS semiconductor device and a low voltage NMOS semiconductor device; and
a second subset of CMOS control elements, each CMOS control element of the second subset of CMOS control elements comprising a high voltage PMOS semiconductor device and a low voltage PMOS semiconductor device.

20. The electronic device of claim 13 , wherein each CMOS control element of the plurality of CMOS control elements comprises semiconductor devices, the plurality of CMOS control elements each comprising:
a PMOS semiconductor device portion comprising a high voltage PMOS semiconductor device and a low voltage PMOS semiconductor device; and
an NMOS semiconductor device portion comprising a high voltage NMOS semiconductor device and a low voltage NMOS semiconductor device.

Assignees

• Invensense Inc

Inventors

• Salvia James Christian
• Perrott Michael H
• Voros Marian
• NG Eldwin
• Tsai Julius Ming-Lin
• Apte Nikhil

Classifications

• G06V40/1359

  Extracting features related to ridge properties; Determining the fingerprint type, e.g. whorl or loop · CPC title

• B06B1/0622 Primary

  on one surface · CPC title

• G06V40/1306

  non-optical, e.g. ultrasonic or capacitive sensing · CPC title

• G06V40/1376

  Matching features related to ridge properties or fingerprint texture · CPC title

• G06F3/03547

  Touch pads, in which fingers can move on a surface · CPC title