Plurality of filters

US11440009B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11440009-B2
Application numberUS-201616097460-A
CountryUS
Kind codeB2
Filing dateJul 15, 2016
Priority dateJul 15, 2016
Publication dateSep 13, 2022
Grant dateSep 13, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method may include etching a number of holes into a carrier wafer layer to form a plurality of filters in the carrier wafer layer, patterning a chamber layer over a first side of the carrier wafer layer to form chambers above each filter formed in the carrier wafer layer, forming a layer over the chamber layer, grinding a second side of the carrier wafer layer to expose the number of holes etched into the carrier wafer layer, and bonding a molded substrate to the carrier wafer layer opposite the chamber layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A fluidic microelectromechanical system (MEMS) device, comprising: a substrate; a die bonded to the substrate; and a top layer bonded to the die opposite the substrate, wherein the top layer and the substrate each comprise a wall to form a chamber to retain an analyte between the top layer and substrate within the MEMS device; a number of measurement electrodes disposed within the chamber; a number of stand-off features disposed within the chamber, wherein the number of stand-off features: are not a full height of the chamber; and form a lattice structure wherein smaller components of an analyte pass between sections of the lattice structure; and a crossflow microfluidic channel comprising a flowing inert fluid, wherein the crossflow microfluidic channel is perpendicular to the chamber to draw, via crossflows, the analyte away from the chamber; wherein the die comprises a plurality of filters with each filter comprising a number of holes defined through the die perpendicular to a plane formed by the substrate; and wherein an interface between the substrate, die, and top layer creates a serpentine fluidic flow through the plurality of filters. 2. The fluidic MEMS device of claim 1 , further comprising a second filter defined in an intermediate top layer above the die, the second filter being stacked above a filter in the die. 3. The fluidic MEMS device of claim 1 , wherein the stand-off features are disposed above a filter in the die. 4. The fluidic MEMS device of claim 3 , wherein a spacing between the number of standoff stand-off features is greater than a spacing between the number of holes of the filter. 5. The fluidic MEMS device of claim 1 , wherein the plurality of filters comprises a first filter and a second filter. 6. The fluidic MEMS device of claim 5 , wherein the second filter is downstream of the first filter. 7. The fluidic MEMS device of claim 6 , wherein the first filter filters out from the analyte introduced into the MEMS device a first sized component of the analyte and wherein the second filter filters out from the analyte a second sized component of the analyte. 8. The fluidic MEMS device of claim 4 , wherein the crossflow microfluidic channel perpendicular to the chamber is between the first and second filters to cause the second sized component of the analyte to be drawn away from the plurality of filters through the fluidic MEMS device to another portion of the fluidic MEMs device for further processing. 9. The fluidic MEMS device of claim 6 , further comprising a number of horizontal filters defined in a chamber between the first and second filters to prevent a first sized component of the analyte from contacting the second filter. 10. The fluidic MEMS device of claim 9 , wherein the analyte is passed through a bottom surface of the first filter, a top surface of the second filter, and a bottom surface of the third filter. 11. A method, comprising: etching a number of holes into a carrier wafer layer to form a plurality of filters in the carrier wafer layer; patterning a chamber layer over a first side of the carrier wafer layer to form chambers above each filter formed in the carrier wafer layer; forming a top layer over the chamber layer; forming a number of stand-off features within the chamber, wherein the number of stand-off features: are not a full height of the chamber; and form a lattice structure wherein smaller components of an analyte pass between sections of the lattice structure; forming an intermediate top layer filter within a chamber and defined in the top layer; grinding a second side of the carrier wafer layer to expose the number of holes etched into the carrier wafer layer; bonding a molded substrate to the carrier wafer layer opposite the chamber layer; and forming a crossflow microfluidic channel comprising a flowing inert fluid, wherein the crossflow microfluidic channel is perpendicular to the chamber to draw, via crossflows, the analyte away from the chamber. 12. The method of claim 11 , further comprising filling etched holes with a protective material. 13. The method of claim 11 , further comprising etching a first and a second filters into the carrier wafer layer. 14. The method of claim 11 , wherein grinding the carrier wafer layer comprises grinding the carrier wafer layer to a thickness of 50 μm to 150 μm. 15. The method of claim 11 , wherein etching the carrier wafer layer further comprises forming an electrode between two of the filters, and wherein the electrode is a pump electrode to pump the analyte through the filters. 16. The method of claim 11 , wherein the crossflow microfluidic channel is formed between two of the formed filters in the carrier wafer layer. 17. A device, comprising: a plurality of filters formed vertically through a silicon layer of the device, wherein the plurality of filters have different vertical heights; a number of cross-flowing microfluidic channels placed between at least two of the filters, wherein: filters in a first cross-flowing microfluidic channel have a first spacing and filters in a second cross-flowing microfluidic channel have a second spacing; a top layer bonded to the silicon layer and a substrate bonded to the silicon layer each comprise walls to form a chamber retain an analyte between the top layer and substrate within the device; a number of stand-off features disposed within the chamber, wherein the number of stand-off features: are not a full height of the chamber; and form a lattice structure wherein smaller components of the analyte pass between sections of the lattice structure; an inert fluid within a perpendicular crossflow microfluidic channel to draw, via crossflows, the analyte away from the chamber; a number of horizontal filters formed on the silicon layer to direct, via crossflows, the analyte to another filter; a number of electrodes, acting as pumps, formed on the silicon layer of the device within the microfluidic channels; wherein the plurality of filters each comprise a number of holes defined through their respective layer. 18. The device of claim 17 , wherein: the number of horizontal filters are upstream of the number of electrodes; and the number of stand-off features are formed on the silicon layer of the device within the microfluidic channels and downstream of the number of electrodes. 19. The device of claim 17 , wherein the number of holes of the plurality of filters comprise a filter hole standoff layer to enable first sized components of the analyte to flow through the filter while preventing second sized components of the analyte from obstructing the flow of the first sized components through the filter. 20. The device of claim 19 , wherein each of the plurality of filters sequentially filter out of the analyte relatively smaller components of the analyte as the analyte passes through the plurality of filters.

Assignees

Inventors

Classifications

  • Purification arrangements, e.g. solid phase extraction [SPE] · CPC title

  • with flat filtering elements (B01D29/39 takes precedence) · CPC title

  • Blanket removal, e.g. polishing · CPC title

  • characterised by the manufacture of the container or its components · CPC title

  • Bonding two components · CPC title

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Frequently asked questions

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What does patent US11440009B2 cover?
A method may include etching a number of holes into a carrier wafer layer to form a plurality of filters in the carrier wafer layer, patterning a chamber layer over a first side of the carrier wafer layer to form chambers above each filter formed in the carrier wafer layer, forming a layer over the chamber layer, grinding a second side of the carrier wafer layer to expose the number of holes et…
Who is the assignee on this patent?
Hewlett Packard Development Co
What technology area does this patent fall under?
Primary CPC classification B01L3/502753. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Sep 13 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).