Method to operate an optical sensor arrangement with improved conversion accuracy and optical sensor arrangement

Patent metadata

Field	Value
Publication number	US-11438006-B2
Application number	US-201816955343-A
Country	US
Kind code	B2
Filing date	Dec 18, 2018
Priority date	Dec 21, 2017
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

An optical sensor arrangement comprises a photodiode and a converter arrangement including an integration amplifier, a comparator amplifier, an integration capacitor and a result register. During a precharge phase the result register is set to a starting value. During an integration phase a current is sampled through the photodiode to update the result register in response to down charges applied to an input of the integration amplifier. During a residue phase the result register is updated in dependence on the charge remaining on the integration capacitor. Measuring the residual charge increases resolution and accuracy of the converter.

First claim

The invention claimed is:

1. A method to operate an optical sensor arrangement,
the optical sensor arrangement comprising:
a photodiode;
a converter arrangement, comprising:
an integration amplifier and a comparator amplifier;
an integration capacitor coupled to an input of the integration amplifier;
a comparator capacitor coupled to an input of the comparator amplifier;

a controller to operate the converter arrangement; and
a result register;

the method comprising performing:
a precharge phase to set the result register to a starting value;
an integration phase to sample a current through the photodiode and update the result register in response to down charges applied to an input of the integration amplifier; and
a residue phase to update the result register in dependence on the charge remaining on the integration capacitor,

wherein the method further comprises at least one of performing a precharge phase or performing a residue phase,
the performing a precharge phase comprises:
setting an output of the integration amplifier to a reference potential;
applying a predetermined charge to change the potential at the output of the integration amplifier;
performing a search algorithm to return the output of the integrator to the reference potential; and
applying another predetermined charge to change the potential at the output of the integration amplifier and setting the result register in response to the other predetermined charge,

the performing a residue phase comprises:
performing a search algorithm to return the output of the integrator to a reference potential; and
applying a predetermined charge to change the potential at the output of the integrating amplifier and setting the result register in response to the predetermined charge.

2. The method according to claim 1 , wherein performing a precharge phase further comprises:
applying a down charge to the input of the integration amplifier and performing a ½ bit per step search algorithm to return the output of the integrator to the reference potential.

3. The method according to claim 1 , wherein applying a predetermined charge comprises applying a down charge to lower the output of the integration amplifier by ¼ count and applying another predetermined charge comprises applying a down charge to lower the output of the integration amplifier by ½ count and setting the result register to +0.5 counts.

4. The method according to claim 1 , wherein performing an integration phase comprises:
connecting the photodiode to the input of the integration amplifier;
comparing the output of the integration amplifier with a reference potential; and
updating the result register in response to the comparing.

5. The method according to claim 4 , wherein performing an integration phase comprises repetitively performing comparing the output of the integration amplifier with a reference potential and changing the result register during a predetermined integration time.

6. The method according to claim 1 , wherein performing a residue phase further comprises:
performing a ½ bit per step search algorithm to return the output of the integrator to the reference potential and updating the result register by an amount proportional to one of an up charge and a down charge applied to the input of the integration amplifier during the step of performing a ½ bit per step search algorithm.

7. The method according to claim 2 , wherein the step of performing a ½ bit per step search algorithm to return the output of the integrator to the reference potential comprises: connecting the comparator capacitor to the output of the integration amplifier and comparing an output signal of the integration amplifier with a reference potential;
applying one of a down charge and an up charge and, in dependence on the result of comparing, applying a lift potential to another input of the integration amplifier.

8. An optical sensor arrangement, comprising:
a photodiode;
a converter arrangement, comprising:
an integration amplifier and a comparator amplifier;
an integration capacitor coupled to an input of the integration amplifier;
a comparator capacitor coupled to an input of the comparator amplifier;

a controller to operate the converter arrangement; and
a result register;
the converter arrangement configured to
set the result register to a starting value during a precharge phase;
update the result register in response to down charges applied to an input of the integration amplifier in response to sampling a current through the photodiode during an integration phase; and
update the result register in dependence on the charge remaining on the integration capacitor during a residue phase, wherein
the converter arrangement is configured to perform a search algorithm to return an output of the integration amplifier to a reference potential during the precharge phase and during the residue phase, and/or
the converter arrangement is configured to adopt one or more of a residue down charge configuration, a residue up charge configuration and a residue lift charge configuration during the precharge phase and during the residue phase.

9. The optical sensor arrangement according to claim 8 ,
wherein, in the residue down charge configuration, a charge redistribution capacitor is connected to the input of the integration amplifier and to a reference potential and another input of the integration amplifier is connected to ground potential.

10. The optical sensor arrangement according to claim 8 ,
wherein, in the residue up charge configuration, a charge redistribution capacitor is connected to the input of the integration amplifier and to ground potential and another input of the integration amplifier is connected to ground potential.

11. The optical sensor arrangement according to claim 8 ,
wherein, in the residue lift charge configuration, a charge redistribution capacitor is connected to ground potential and to the input of the integration amplifier and another input of the integration amplifier is connected to a lift potential.

12. The optical sensor arrangement according to claim 8 ,
wherein the converter arrangement is configured to perform a precharge phase comprising:
setting an output of the integration amplifier to a reference potential;
applying a predetermined charge to change the potential at the output of the integration amplifier by applying a down charge to the input of the integration amplifier to lower the output of the integration amplifier by a first count value;
performing a search algorithm to return the output of the integrator to the reference potential by performing a search algorithm to return the output of the integrator to the reference potential; and
applying another predetermined charge to change the potential at the output of the integration amplifier by applying a down charge to lower the output of the integration amplifier by a second count value and setting the result register in response to the other predetermined charge;
wherein the converter arrangement is configured to perform an integration phase comprising:
connecting the photodiode to the input of the integration amplifier;
comparing the output of the integration amplifier with the reference potential; and
updating the result register in response to the step of comparing; and
wherein the converter arrangement is configured to perform a residue phase comprising:
performing a search algorithm to return the output of the integrator to the reference potential; and
applying a predetermined charge to change the potential at the output of the integrating amplifier and setting the result register in response to th

Assignees

• Ams Int Ag

Inventors

• Williams Iii Louis Albert
• Han Yong

Classifications

• H03M1/52 Primary

  Input signal integrated with linear return to datum · CPC title

• G01J2001/444

  Compensating; Calibrating, e.g. dark current, temperature drift, noise reduction or baseline correction; Adjusting · CPC title

• G01J1/46

  using a capacitor · CPC title

• G01J2001/446

  Photodiode · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title