Semiconductor device and power conversion device

Patent metadata

Field	Value
Publication number	US-11437505-B2
Application number	US-201916968233-A
Country	US
Kind code	B2
Filing date	Feb 19, 2019
Priority date	Mar 15, 2018
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

Even when a stress is applied due to energization or switching operation, a connection state of electrode layers can be appropriately maintained. A semiconductor device includes a semiconductor layer of first conductivity type, an upper surface structure formed on a surface layer of the semiconductor layer, and an upper surface electrode formed over the upper surface structure. The upper surface electrode includes a first electrode formed on an upper surface of the semiconductor layer, and a second electrode formed over an upper surface of the first electrode. The first concave portion is formed on the upper surface of the first electrode. A side surface of the first concave portion has a tapered shape. The second electrode is formed over the upper surface of the first electrode including an inside of the first concave portion.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor layer of first conductivity type;
an upper surface structure formed at least on a surface layer of the semiconductor layer; and
an upper surface electrode formed over at least the upper surface structure, wherein
the upper surface electrode includes
a first electrode formed on at least an upper surface of the semiconductor layer, and
a second electrode formed over an upper surface of the first electrode,

at least one first concave portion is formed on the upper surface of the first electrode,
a side surface of the first concave portion has a tapered shape,
the second electrode is formed over the upper surface of the first electrode including an inside of the first concave portion,
the semiconductor device further comprises a second concave portion penetrating the upper surface of the first electrode including an inside of the first concave portion, and having a width smaller than that of the first concave portion and a depth less than a thickness of the first electrode, and
the second concave portion is formed on a slope in the first concave portion.

2. A semiconductor device comprising:
a semiconductor layer of first conductivity type;
an upper surface structure formed at least on a surface layer of the semiconductor layer; and
an upper surface electrode formed over at least the upper surface structure, wherein
the upper surface electrode includes
a first electrode formed on at least an upper surface of the semiconductor layer, and
a second electrode formed over an upper surface of the first electrode,

at least one first concave portion is formed on the upper surface of the first electrode,
a side surface of the first concave portion has a tapered shape,
the second electrode is formed over the upper surface of the first electrode including an inside of the first concave portion, and
the semiconductor device further comprises a second concave portion penetrating the upper surface of the first electrode in a portion where the first concave portion is not formed, and having a width smaller than that of the first concave portion and a depth less than a thickness of the first electrode.

3. The semiconductor device according to claim 1 , wherein
an angle between a side surface of the first concave portion and the upper surface of the semiconductor layer is 5° or more.

4. The semiconductor device according to claim 1 , wherein
the angle between a side surface of the first concave portion and the upper surface of the semiconductor layer is 60° or less.

5. The semiconductor device according to claim 1 , wherein
a number of the first concave portions formed on the upper surface of the first electrodes is 100 or more.

6. The semiconductor device according to claim 1 , wherein
a number of the second concave portions arranged per 1 μm 2 is one or more.

7. The semiconductor device according to claim 1 , wherein
the first concave portion has a width of 0.1 μm or more and the second concave portion has a width of less than 0.1 μm.

8. The semiconductor device according to claim 1 , wherein
the upper surface structure includes
a base region of second conductivity type selectively formed on the surface layer of the semiconductor layer,
a source region of first conductive type selectively formed on a surface layer of the base region,
a gate electrode formed in contacting with the base region interposed between the source region and the first semiconductor layer via a gate insulating film,
an interlayer insulating film formed over the gate electrode.

9. The semiconductor device according to claim 8 , wherein
an angle between a side surface of the interlayer insulating film and the upper surface of the semiconductor layer is larger than the angle between a side surface of the first concave portion and the upper surface of the semiconductor layer.

10. A power conversion device comprising:
a conversion circuit including the semiconductor device according to claim 1 , and configured to convert input power and output the power;
a drive circuit configured to output a drive signal for driving the semiconductor device to the semiconductor device; and
a control circuit configured to output a control signal for controlling the drive circuit to the drive circuit.

11. The semiconductor device according to claim 2 , wherein
an angle between a side surface of the first concave portion and the upper surface of the semiconductor layer is 5° or more.

12. The semiconductor device according to claim 2 , wherein
the angle between a side surface of the first concave portion and the upper surface of the semiconductor layer is 60° or less.

13. The semiconductor device according to claim 2 , wherein
a number of the first concave portions formed on the upper surface of the first electrodes is 100 or more.

14. The semiconductor device according to claim 2 , wherein
a number of the second concave portions arranged per 1 μm 2 is one or more.

15. The semiconductor device according to claim 2 , wherein
the first concave portion has a width of 0.1 μm or more and the second concave portion has a width of less than 0.1 μm.

16. The semiconductor device according to claim 2 , wherein
the upper surface structure includes
a base region of second conductivity type selectively formed on the surface layer of the semiconductor layer,
a source region of first conductive type selectively formed on a surface layer of the base region,
a gate electrode formed in contacting with the base region interposed between the source region and the first semiconductor layer via a gate insulating film, and
an interlayer insulating film formed over the gate electrode.

17. The semiconductor device according to claim 16 , wherein
an angle between a side surface of the interlayer insulating film and the upper surface of the semiconductor layer is larger than the angle between a side surface of the first concave portion and the upper surface of the semiconductor layer.

18. A power conversion device comprising:
a conversion circuit including the semiconductor device according to claim 2 , and configured to convert input power and output the power;
a drive circuit configured to output a drive signal for driving the semiconductor device to the semiconductor device; and
a control circuit configured to output a control signal for controlling the drive circuit to the drive circuit.

Assignees

• Mitsubishi Electric Corp

Inventors

• Nakata Kazunari
• Taguchi Kensuke

Classifications

• H10P14/46

  using a liquid · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D64/252

  for vertical or pseudo-vertical devices · CPC title

• H10D62/8325 Primary

  Silicon carbide · CPC title

• H02M7/003

  Constructional details, e.g. physical layout, assembly, wiring or busbar connections · CPC title