Power semiconductor device

Patent metadata

Field	Value
Publication number	US-11437471-B2
Application number	US-202017118693-A
Country	US
Kind code	B2
Filing date	Dec 11, 2020
Priority date	Dec 20, 2019
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

A power semiconductor device includes: a semiconductor body; a first load terminal structure coupled to the body front side and a second load terminal structure coupled to the body backside; an active area for conducting a load current between the load terminal structures; a drift region having a first conductivity type; a backside region arranged at the backside and including, inside the active area, first and second backside emitter zones. At least one of the backside emitter zones includes: first sectors each having at least one first region of a second conductivity type, the first region arranged in contact with the second load terminal structure and having a smallest lateral extension of at most 50 μm; and/or second sectors each having a second region of the second conductivity type arranged in contact with the second load terminal structure and having a smallest lateral extension of at least 50 μm.

First claim

What is claimed is:

1. A power semiconductor device, comprising:
a semiconductor body having a front side and a backside;
a first load terminal structure coupled to the front side and a second load terminal structure coupled to the backside;
an active area of the semiconductor body configured to conduct a load current between the first load terminal structure and the second load terminal structure;
a drift region of the semiconductor body having a first conductivity type and configured to conduct the load current;
a backside region of the semiconductor body arranged at the backside and comprising, inside the active area, a first backside emitter zone and a second backside emitter zone, wherein at least one of the first backside emitter zone and the second backside emitter zone comprises:
a plurality of first sectors each comprising at least one first region of a second conductivity type arranged in contact with the second load terminal structure and having a smallest lateral extension of at most 50 μm; and/or
a plurality of second sectors each consisting of a second region of the second conductivity type arranged in contact with the second load terminal structure and having a smallest lateral extension of at least 50 μm;

wherein the second backside emitter zone differs from the first backside emitter zone at least in one of the following:
the presence of the first sectors;
the presence of the second sectors;
the smallest lateral extension of the first sectors;
the smallest lateral extension of the second sectors;
a lateral distance between neighboring first sectors;
a lateral distance between neighboring second sectors;
a smallest lateral extension of the first regions; and
a lateral distance between neighboring first regions within the same first sector.

2. The power semiconductor device of claim 1 , wherein an area extension of each of the first backside emitter zone and the second backside emitter zone amounts to at least 5% of the active area.

3. The power semiconductor device of claim 1 , wherein a lateral distance between neighboring first and/or second sectors amounts to at least 50 μm.

4. The power semiconductor device of claim 1 , wherein the first backside emitter zone and/or the second backside emitter zone comprises a plurality of first sectors, wherein each of the first sectors comprises a plurality of first regions, the first regions being arranged at a lateral distance from each other of at most three times the smallest lateral extension of the first regions.

5. The power semiconductor device of claim 1 , wherein:
the first backside emitter zone comprises a plurality of first sectors, each of the first sectors comprising a plurality of first regions, the first regions being arranged at a lateral distance from each other of at most three times the smallest lateral extension of the first regions; and
the second backside emitter zone comprises a region of the first conductivity type forming a contiguous contact with the second load terminal structure and having a lateral extension of at least ten times the smallest lateral extension of the first regions.

6. The power semiconductor device of claim 1 , wherein:
the first backside emitter zone comprises a plurality of first sectors, each of the first sectors comprising a plurality of first regions, the first regions being arranged at a lateral distance from each other of at most three times the smallest lateral extension of the first regions; and
the second backside emitter zone comprises a plurality of second sectors each comprising a second region having a smallest lateral extension of at least ten times the smallest lateral extension of the first regions.

7. The power semiconductor device of claim 1 , wherein the backside region further comprises a third backside zone which comprises a plurality of regions of the first conductivity type and a plurality of regions of the second conductivity type arranged in alternating order in contact with the second load terminal structure, the regions of the first conductivity type and the regions of the second conductivity type having a smallest lateral extension of at most 50 μm.

8. The power semiconductor device of claim 7 , wherein the third backside zone is arranged in an edge termination region of the semiconductor body.

9. The power semiconductor device of claim 7 , wherein the third backside zone is arranged below a gate runner electrode that is arranged at the front side.

10. The power semiconductor device of claim 7 , wherein a lateral extension of the third backside zone amounts to at least 0.5 times a vertical thickness of the drift region.

11. A power semiconductor device, comprising:
a semiconductor body having a front side and a backside;
a first load terminal structure coupled to the front side and a second load terminal structure coupled to the backside;
an active area of the semiconductor body configured to conduct a load current between the first load terminal structure and the second load terminal structure;
a drift region of the semiconductor body having a first conductivity type and configured to conduct the load current;
a backside region of the semiconductor body arranged at the backside and comprising, inside the active area, a first backside emitter zone and a second backside emitter zone,
wherein at least one of the first backside emitter zone and the second backside emitter zone comprises: a plurality of second sectors each comprising a second region of the second conductivity type, the second regions being arranged in contact with the second load terminal structure and having a smallest lateral extension of at least 50 μm;
wherein the first backside emitter zone has each of a first emitter efficiency and a first injection efficiency;
wherein the second backside emitter zone has each of a second emitter efficiency and a second injection efficiency at the nominal current;
wherein:
the first emitter efficiency differs from the second emitter efficiency by at least 1%; and/or
the first injection efficiency differs from the second injection efficiency by at least 5%; and/or
an injected hole charge of the first backside emitter zone differs from an injected hole charge of the second backside emitter zone by at least 10%; and/or
an average backside plasma concentration associated with the first backside emitter zone differs from an average backside plasma concentration associated with the second backside emitter zone by at least 5%.

12. A power semiconductor device, comprising:
a semiconductor body having a front side and a backside;
a first load terminal structure coupled to the front side and a second load terminal structure coupled to the backside;
an active area of the semiconductor body configured to conduct a load current between the first load terminal structure and the second load terminal structure;
a drift region of the semiconductor body having a first conductivity type and configured to conduct the load current;
a backside region of the semiconductor body arranged at the backside and comprising, inside the active area, a first backside emitter zone and a second backside emitter zone,
wherein each of the first backside emitter zone and the second backside emitter zone comprises a plurality of regions of a second conductivity type arranged in contact with the second load terminal structure and a plurality of regions of the first conductivity type arranged in contact with the second load terminal structure;
wherein a dopant concentration in a respective central portion of the regions of the second conductivity type in the first backside emitter zone is essentially equal to a dopant concentration in

Assignees

• Infineon Technologies Ag

Inventors

• Baburske Roman
• Hauf Moritz
• Schulze Hans-Joachim
• Schulze Holger
• Stoib Benedikt

Classifications

• H10D62/129

  Cathode regions of diodes · CPC title

• H10D84/617

  Combinations of vertical BJTs and only diodes · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/112

  for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers · CPC title

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title