Array substrate having detection and compensation lead lines, display apparatus, method of fabricating array substrate, and pixel driving circuit having connection bridge

Patent metadata

Field	Value
Publication number	US-11437440-B2
Application number	US-201916963346-A
Country	US
Kind code	B2
Filing date	Sep 27, 2019
Priority date	Jul 5, 2019
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

An array substrate includes an array of a plurality of subpixels including a plurality of columns of subpixels respectively spaced apart by a plurality of inter-subpixel regions; a plurality of pixel driving circuits respectively driving light emission of the plurality of subpixels; and a plurality of detection and compensation lead lines respectively configured to respectively detect signals in the plurality of subpixels and respectively compensate signals in the plurality of subpixels. A respective one of a plurality of detection and compensation lead lines is disposed in a first inter-subpixel region between two directly adjacent columns of subpixels. The respective one of the plurality of detection and compensation lead lines is spaced apart by at least one columns of subpixels from a signal line configured to transmit an alternating current and arranged along a direction parallel to the respective one of the plurality of detection and compensation lead lines.

First claim

What is claimed is:

1. An array substrate comprising:
an array of a plurality of subpixels comprising a plurality of columns of subpixels respectively spaced apart by a plurality of inter-subpixel regions;
a plurality of pixel driving circuits respectively driving light emission of the plurality of subpixels; and
a plurality of detection and compensation lead lines respectively configured to respectively detect signals in the plurality of subpixels and respectively compensate signals in the plurality of subpixels;
wherein one of a plurality of detection and compensation lead lines electrically connects a respective one of the plurality of pixel driving circuits to a data detection and compensation circuit;
a respective one of the plurality of detection and compensation lead lines is disposed in a first inter-subpixel region between two directly adjacent columns of subpixels; and
the respective one of the plurality of detection and compensation lead lines is spaced apart by at least one columns of subpixels from a signal line configured to transmit an alternating current and arranged along a direction parallel to the respective one of the plurality of detection and compensation lead lines.

2. The array substrate of claim 1 , further comprising a plurality of data lines configured to respectively transmit data signals to the plurality of subpixels;
wherein the plurality of data lines and the plurality of detection and compensation lead lines are arranged along a substantially same direction; and
the respective one of the plurality of detection and compensation lead lines is spaced apart by at least one columns of subpixels from any data line.

3. The array substrate of claim 2 , wherein, in at least a second inter-subpixel region of the plurality of inter-subpixel regions, two data lines of the plurality of data lines are in a same inter-subpixel region between two directly adjacent columns of sub pixels.

4. The array substrate of claim 1 , further comprising a plurality of low voltage signal lines configured to provide a low voltage signal to a cathode of a light emitting element in a respective one of the plurality of subpixels;
wherein the plurality of low voltage signal lines and the plurality of detection and compensation lead lines are arranged along a substantially same direction; and
a respective one of the plurality of low voltage signal lines and the respective one of the plurality of detection and compensation lead lines are in a same inter-subpixel region between two directly adjacent columns of subpixels.

5. The array substrate of claim 1 , further comprising a plurality of power supply lines configured to provide a high voltage signal to a respective one of the plurality of pixel driving circuit;
wherein the plurality of power supply lines and the plurality of detection and compensation lead lines are arranged along a substantially same direction;
a respective one of the plurality of power supply lines is disposed in a third inter-subpixel region between two directly adjacent columns of subpixels; and
the third inter-subpixel region is spaced apart from the first inter-subpixel region by at least one columns of subpixels.

6. The array substrate of claim 5 , wherein N columns of the plurality of columns of subpixels, N number of data lines of a plurality of data lines, the respective one of the plurality of detection and compensation lead lines, and a respective one of a plurality of low voltage signal lines are disposed between two most adjacent power supply lines of the plurality of power supply lines, N >2.

7. The array substrate of claim 6 , wherein the respective one of the plurality of detection and compensation lead lines and the respective one of the plurality of low voltage signal lines are disposed in a central-most inter-subpixel region between two adjacent central-most columns of the N columns of the plurality of columns of subpixels; and
in at least a second inter-subpixel region of the plurality of inter-subpixel regions, two data lines of the plurality of data lines are in a same inter-subpixel region between two directly adjacent columns of subpixels.

8. The array substrate of claim 1 , further comprising a plurality of detection and compensation lines electrically connected to the plurality of detection and compensation lead lines;
wherein a respective one of the plurality of detection and compensation lines electrically connects pixel driving circuits in a respective row of subpixels to the data detection and compensation circuit; and
a respective one of the plurality of detection and compensation lines is disposed in an inter-subpixel region between two directly adjacent rows of subpixels.

9. The array substrate of claim 8 , wherein a respective one of the plurality of pixel driving circuits comprises a storage capacitor;
the storage capacitor comprises a first capacitor and a second capacitor electrically connected in parallel;
the first capacitor comprises a semiconductor electrode layer, a first capacitor electrode, and an insulating layer between the semiconductor electrode layer and the first capacitor electrode; and
the second capacitor comprises the semiconductor electrode layer, a second capacitor electrode, and an inter-layer dielectric layer between the semiconductor electrode layer and the second capacitor electrode;
wherein the first capacitor electrode is configured to at least partially shield light irradiating on an active layer of a thin film transistor in the respective one of the plurality of pixel driving circuits;
an orthographic projection of the first capacitor electrode on a base substrate at least partially overlapping with an orthographic projection of the active layer of the thin film transistor in the respective one of the plurality of pixel driving circuits on the base substrate; and
the second capacitor electrode is in a same layer as a source electrode of the thin film transistor in the respective one of the plurality of pixel driving circuits.

10. The array substrate of claim 9 , wherein the respective one of the plurality of pixel driving circuits further comprises a driving thin film transistor and a switching thin film transistor;
a source electrode of the switching thin film transistor is connected to a respective one of a plurality of data lines;
a drain electrode of the switching thin film transistor is connected to the semiconductor electrode layer;
a gate electrode of the switching thin film transistor is connected to a respective one of a plurality of first gate lines;
a source electrode of the driving thin film transistor is connected to a respective one of a plurality of power supply lines;
a drain electrode of the driving thin film transistor is connected to a light emitting element in a respective one of the plurality of subpixels; and
a gate electrode of the driving thin film transistor is connected to a drain electrode of the switching thin film transistor;
wherein the semiconductor electrode layer and an active layer of the switching thin film transistor are parts of a unitary structure;
the respective one of the plurality of pixel driving circuits comprises a connection bridge electrically connecting the semiconductor electrode layer and the active layer of the switching thin film transistor;
the connection bridge is on a side of an extension portion of the gate electrode of the driving thin film transistor away from the base substrate;
the connection bridge comprises a first portion in direct contact with the extension portion of the gate electrode of the driving thin film transistor, a second portion in direct contact with the semiconductor electrode layer, and a third portion in direct contact with the

Assignees

• Hefei Boe Joint Tech Co Ltd
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Yuan Can
• Li Yongqian
• Xu Pan
• Yuan Zhidong
• Li Meng
• Feng Xuehuan
• Ding Zehua

Classifications

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/043

  Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver · CPC title

• G09G3/3225

  using an active matrix · CPC title

• G09G2300/0452

  Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title