Epitaxies of a chemical compound semiconductor

Patent metadata

Field	Value
Publication number	US-11437235-B2
Application number	US-202017093865-A
Country	US
Kind code	B2
Filing date	Nov 10, 2020
Priority date	Mar 17, 2014
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.

First claim

What is claimed is:

1. A structure comprising:
a substrate;
a prelayer over the substrate;
a barrier layer over the prelayer, the barrier layer includes one of GaAs and InGaAs; and
a channel layer over the barrier layer;
wherein a concentration of dopant in the barrier layer is in an order of 10 17 cm −3 .

2. The structure of claim 1 , wherein the channel layer includes a pair of layers of common composition and an InAs layer between the pair of layers, the InAs layer of different composition than the pair of layers.

3. The structure of claim 1 , wherein the channel layer is disposed within a transistor.

4. The structure of claim 1 , wherein the barrier layer is slightly P-type or slightly N-type.

5. The structure of claim 1 , wherein the prelayer includes arsenic.

6. A structure comprising:
a substrate;
a prelayer formed over the substrate at a graded temperature;
a barrier layer over the prelayer; and
a channel layer over the barrier layer;
wherein a concentration of dopant in the barrier layer is in an order of 10 17 cm −3 .

7. The structure of claim 6 , wherein the channel layer includes a pair of layers of common composition and an InAs layer between the pair of layers, the InAs layer of different composition than the pair of layers.

8. The structure of claim 6 , wherein the channel layer includes AlSb.

9. The structure of claim 6 , wherein the channel layer includes AlGaSb.

10. The structure of claim 6 , wherein the channel layer includes AlInSb.

11. The structure of claim 6 , wherein the channel layer includes InAs.

12. A structure comprising:
a substrate;
a prelayer over the substrate;
a barrier layer over the prelayer; and
a channel layer over the barrier layer, the channel layer including a heterostructure comprising InAs;
wherein a concentration of dopant in the barrier layer is in an order of 10 17 cm −3 .

13. The structure of claim 12 , wherein the channel layer includes a pair of layers of common composition and an InAs layer between the pair of layers, the InAs layer of different composition than the pair of layers.

14. The structure of claim 12 , wherein heterostructure includes AlSb.

15. The structure of claim 12 , wherein heterostructure includes AlGaSb.

16. The structure of claim 12 , wherein heterostructure includes AlInSb.

17. The structure of claim 12 , wherein heterostructure includes InAs.

18. The structure of claim 12 , wherein the channel layer is disposed within a transistor.

19. The structure of claim 12 , wherein the barrier layer is slightly P-type or slightly N-type.

20. The structure of claim 12 , wherein the prelayer includes arsenic.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Univ National Chiao Tung
• Taiwan Semiconductor Manufacturing Company Limited & National Chiao Tung Univ

Inventors

• Yu Hung-Wei
• Chang Yi
• Wang Tsun-Ming

Classifications

• H10P14/3422

  Antimonides · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/3254

  Graded layers · CPC title

• H10P14/3248

  consisting of two layers · CPC title

• H10P14/3221

  Arsenides · CPC title