Processing device for reducing a load on a system bus

Patent metadata

Field	Value
Publication number	US-11436375-B2
Application number	US-201916526665-A
Country	US
Kind code	B2
Filing date	Jul 30, 2019
Priority date	Jan 31, 2017
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

The application relates to a processing device (100) including a buffer (102) coupled to a system bus, a ciphering device coupled to the system bus, and a memory coupled to the ciphering device. The processing device is configured to operate in at least one of a deciphering mode and a ciphering mode. In the deciphering mode, the ciphering device is configured to receive a ciphered data unit directly from the buffer over the system bus, decipher the ciphered data unit so as to obtain a deciphered data unit, and transfer the deciphered data unit to the memory. In the ciphering mode, the ciphering device is configured to receive a data unit from the memory, cipher the data unit so as to obtain a ciphered data unit, and transfer the ciphered data unit directly to the buffer over the system bus.

First claim

The invention claimed is:

1. A processing device comprising:
a buffer directly coupled to a system bus,
a ciphering device directly coupled to the system bus, and
a memory directly coupled to the ciphering device and directly coupled to the system bus;
wherein the processing device is configured to operate in at least one of a deciphering mode or a ciphering mode;
wherein the ciphering device, when the processing device is configured to operate in the deciphering mode, is configured to:
receive a ciphered data unit (DU) from the buffer over the system bus,
transfer the ciphered data unit to the memory;
decipher the ciphered data unit at an input interface to the memory to obtain a deciphered data unit, and
transfer the deciphered data unit to the memory;
wherein the ciphering device, when the processing device is configured to operate in the ciphering mode, is configured to:
receive a data unit from the memory,
cipher the data unit at an output interface from the memory to obtain a ciphered data unit, and
transfer the ciphered data unit to the buffer over the system bus.

2. The processing device according to claim 1 , wherein the processing device, when configured to operate in the deciphering mode, is further configured to:
read a protocol header carried by a data block (DB) comprising the ciphered data unit,
extract at least one ciphering parameter from the protocol header, and
provide the at least one ciphering parameter to the ciphering device.

3. The processing device according to claim 2 , wherein the ciphering device is further configured to:
receive the ciphering parameter,
decipher the ciphered data unit based on the received ciphering parameter to obtain the deciphered data unit.

4. The processing device according to claim 3 , further configured to:
read the protocol header directly from the buffer.

5. The processing device according to claim 1 , wherein the memory is coupled to the system bus, and wherein the processing device is configured to:
transfer at least one first segment of a ciphered data unit from the buffer to the memory if no protocol header for the ciphered data unit is available.

6. The processing device according to claim 5 , wherein the ciphering device is further configured to:
receive a ciphering parameter for the ciphered data unit,
fetch the first segment of the ciphered data unit from the memory,
receive a second segment of the ciphered data unit directly from the buffer over the system bus, wherein the second segment is a remaining segment of the ciphered data unit;
decipher the first segment and the second segment of the ciphered data unit based on the received ciphering parameter to obtain a deciphered data unit.

7. The processing device according to claim 1 , wherein the system bus is coupled to the memory only through the ciphering device.

8. The processing device according to claim 1 , wherein the buffer is a reception buffer when the processing device is configured to operate in the deciphering mode, and wherein the buffer is a transmission buffer when the processing device is configured to operate in the ciphering mode.

9. The processing device according to claim 8 , wherein the buffer is a Hybrid Automatic Repeat Request buffer.

10. The processing device according to claim 1 , wherein the processing device, when configured to operate in the ciphering mode, is configured to:
cipher the data unit with a ciphering parameter so as to obtain the ciphered data unit, and
transfer the ciphering parameter directly to the buffer over the system bus.

11. The processing device according to claim 10 , wherein the ciphering device is further configured to:
transfer the ciphering parameter in a protocol header of a data block (DB) directly to the buffer.

12. The processing device according to claim 11 , wherein the ciphering device is configured to:
transfer, directly to the buffer, the data block carrying a first segment of the ciphered data unit together with the ciphering parameter in the protocol header, and
transfer, directly to the buffer, another data block carrying a second segment of the ciphered data unit but not carrying the ciphering parameter.

13. The processing device according to claim 1 , wherein the processing device is comprised in a communication device for a communication system.

14. A method for a processing device, the processing device comprising
a buffer directly coupled to a system bus,
a ciphering device directly coupled to the system bus, and
a memory directly coupled to the ciphering device and directly coupled to the system bus;
wherein the processing device is configured to operate in at least one of a deciphering mode or in a ciphering mode, the method comprising:

when the processing device is configured to operate in the deciphering mode,
receiving, by the ciphering device, a ciphered data unit from a buffer over a system bus,
transferring the ciphered data unit to the memory;
deciphering, by the ciphering device, the ciphered data unit at an input interface to the memory so as to obtain a deciphered data unit,
transferring, by the ciphering device, the deciphered data unit to a memory; when the processing device is configured to operate in the ciphering mode,
receiving, by the ciphering device, a data unit from the memory,
ciphering, by the ciphering device, the data unit at an output interface from the memory to obtain a ciphered data unit,
transferring, by the ciphering device, the ciphered data unit to the buffer over the system bus.

15. A computer program product comprising a non-transitory computer-readable medium and computer executable instructions stored on the non-transitory computer-readable medium, wherein when the instructions are executed by a processor, causes the processor to perform operations comprising:
receiving, by a ciphering device directly coupled to a system bus, a ciphered data unit from a buffer over the system bus, the buffer is directly coupled to the system bus;
transferring the ciphered data unit to a memory;
deciphering, by the ciphering device, the ciphered data unit at an input interface to the memory to obtain a deciphered data unit;
transferring, by the ciphering device, the deciphered data unit to the memory, the memory is directly coupled to the ciphering device and directly coupled to the system bus;
receiving, by the ciphering device, a data unit from the memory;
ciphering, by the ciphering device, the data unit at an output interface from the memory so as to obtain a ciphered data unit; and
transferring, by the ciphering device, the ciphered data unit to the buffer over the system bus.

Assignees

• Huawei Tech Co Ltd

Inventors

• Lundgren Thomas
• Uden Johan

Classifications

• H04L63/0428

  wherein the data content is protected, e.g. by encrypting or encapsulating the payload · CPC title

• G06F21/72 Primary

  in cryptographic circuits · CPC title

• G06F13/4208

  being a system bus, e.g. VME bus, Futurebus, Multibus · CPC title

• G06F2221/2107

  File encryption · CPC title

• H04L63/0485 Primary

  Networking architectures for enhanced packet encryption processing, e.g. offloading of IPsec packet processing or efficient security association look-up · CPC title