Storage system and method for using read and write buffers in a memory

Patent metadata

Field	Value
Publication number	US-11435920-B2
Application number	US-202117183703-A
Country	US
Kind code	B2
Filing date	Feb 24, 2021
Priority date	Jan 20, 2021
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.

First claim

What is claimed is:

1. A storage system comprising:
a memory; and
a controller configured to:
receive, from a host, a command for improved read performance for a logical block address range;
in response to receiving the command for improved read performance:
create a read buffer allocated from single-level cell (SLC) blocks in the memory;
copy data stored in multi-level cell (MLC) blocks in the memory associated with the logical block address range into the read buffer; and
create, in a logical-to-physical address data structure, an association between the logical block address range and physical addresses in the read buffer that store the data:

receive a read command from the host for the data;
in response to receiving the read command, send the data stored in the read buffer to the host;
receive, from the host, a command indicating that improved read performance is no longer needed for the logical block address range; and
in response to receiving the command indicating that improved read performance is no longer needed for the logical block address range, remove, from the logical-to-physical address data structure, the association between the logical block address range and physical addresses in the read buffer that store the data.

2. The storage system of claim 1 , wherein the controller is further configured to create the read buffer in response to a number of free blocks in the memory exceeding a threshold.

3. The storage system of claim 1 , wherein the data copied from the MLC blocks is identified by a logical block address received from the host prior to receiving the read command from the host.

4. The storage system of claim 1 , wherein the controller is further configured to copy the data from the MLC blocks after predicting that the host will request the data.

5. The storage system of claim 1 , wherein the controller is further configured to:
delete the data from the MLC blocks after the data has been copied into the read buffer; and
flush the data from the read buffer to the MLC blocks.

6. The storage system of claim 5 , wherein the controller is further configured to flush the data from the read buffer to the MLC blocks in response to a flush command from the host.

7. The storage system of claim 5 , wherein the controller is further configured to flush the data from the read buffer to the MLC blocks in response to a flush policy of the storage system.

8. The storage system of claim 1 , wherein the data is fragmented in the SLC blocks, and wherein the controller is further configured to defragment the data when writing the data to the MLC blocks in response to a flush command.

9. The storage system of claim 1 , further comprising a volatile memory, wherein the controller is further configured to copy, from the memory to the volatile memory, a portion of the logical-to-physical address data structure.

10. The storage system of claim 1 , wherein the controller is further configured to provide an attribute that indicates one or more of following: a maximum size of the read buffer, a fullness of the read buffer, a health of the read buffer, and a health of blocks of the memory not used for the read buffer.

11. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

12. A storage system comprising:
a memory comprising single-level cell (SLC) blocks and multi-level cell (MLC) blocks;
means for receiving, from a host, a command for improved read performance for a logical block address range;
means for in response to receiving the command for improved read performance:
creating a read buffer allocated from single-level cell (SIX) blocks in the memory;
copying data stored in multi-level cell (MIX) blocks in the memory associated with the logical block address range into the read buffer; and
creating, in a logical-to-physical address data structure, an association between the logical block address range and physical addresses in the read buffer that store the data;

means for receiving a read command from the host for the data:
means for sending the data stored in the read buffer to the host in response to receiving the read command:
means for receiving, from the host, a command indicating that improved read performance is no longer needed for the logical block address range; and
means for removing, from the logical-to-physical address data structure, the association between the logical block address range and physical addresses in the read buffer that store the data in response to receiving the command indicating that improved read performance is no longer needed for the logical block address range.

13. In a storage system comprising a memory with single-level cell (SLC) blocks and multi-level cell (MLC) blocks, a method comprising:
receiving, from a host, a command for improved read performance for a logical block address range;
in response to receiving the command for improved read performance:
creating a read buffer allocated from single-level cell (SLC) blocks in the memory;
copying data stored in multi-level cell (MLC) blocks in the memory associated with the logical block address range into the read buffer; and
creating, in a logical-to-physical address data structure, an association between the logical block address range and physical addresses in the read buffer that store the data;

receiving a read command from the host for the data;
in response to receiving the read command, sending the data stored in the read buffer to the host;
receiving, from the host, a command indicating that improved read performance is no longer needed for the logical block address range; and
in response to receiving the command indicating that improved read performance is no longer needed for the logical block address range, removing, from the logical-to-physical address data structure, the association between the logical block address range and physical addresses in the read buffer that store the data.

14. The method of claim 13 , further comprising creating the read buffer in response to a number of free blocks in the memory exceeding a threshold.

15. The method of claim 13 , wherein the data copied from the MLC blocks is identified by a logical block address received from the host prior to receiving the read command from the host.

16. The method of claim 13 , further comprising copying the data from the MLC blocks after predicting that the host will request the data.

17. The method of claim 13 , further comprising:
deleting the data from the MLC blocks after the data has been copied into in the read buffer; and
flushing the data from the read buffer to the MLC blocks.

18. The method of claim 17 , further comprising flushing the data from the read buffer to the MLC blocks in response to a flush command from the host.

19. The method of claim 17 , further comprising flushing the data from the read buffer to the MIX blocks in response to a flush policy of the storage system.

20. The method of claim 13 , wherein the data is fragmented in the SLC blocks, and wherein the method further comprises defragmenting the data when writing the data to the MLC blocks in response to a flush command.

Assignees

• Western Digital Tech Inc

Inventors

• Sela Rotem
• Zilberstein Einav
• Inbar Karin

Classifications

• G06F2212/7204

  Capacity control, e.g. partitioning, end-of-life degradation · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title