Two-capacitor digital-to-analog converter

Patent metadata

Field	Value
Publication number	US-11431348-B2
Application number	US-202117248840-A
Country	US
Kind code	B2
Filing date	Feb 10, 2021
Priority date	Feb 21, 2020
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A two-capacitor digital-to-analog converter circuit having circuitry to compensate for an unwanted capacitance is disclosed. The converter is configured to generate an average voltage on two capacitors for a sequence of bits in a digital word so that when the final bit is reached, the average voltage corresponds to an analog level of the digital word. The converter is configured to input and average the voltage on the two capacitors using different modes to minimize the effects of capacitor mismatch and switching capacitance on the accuracy of the conversion. The converter includes a buffer amp that has an input capacitance that can affect the conversion. Accordingly, the converter further includes capacitance compensation circuitry configured to provide a replica input capacitance that can be charged and discharged according to the bits of the digital word and coupled to the input capacitor to prevent the input capacitance from affecting the conversion.

First claim

The invention claimed is:

1. A two-capacitor digital-to-analog converter circuit, comprising:
a phase and mode controller configured to set an active bit in a digital word, select a mode condition for the active bit, and configure switches according to a first mode or a second mode of a conversion process based on a value of the active bit and the selected mode condition;
a first capacitor directly coupled between a first terminal of a redistribution switch and a ground, the first terminal of the redistribution switch coupled to a first set of switches controlled by the phase and mode controller;
a second capacitor directly coupled between a second terminal of the redistribution switch and the ground, the second terminal of the redistribution switch coupled to a second set switches controlled by the phase and mode controller, wherein the redistribution switch is configured to, during a redistribution phase of the conversion process, couple the first capacitor and the second capacitor together to generate a redistribution voltage;
a buffer amp configured to generate an output voltage based on the redistribution voltage, the buffer amp having an input capacitance at an input; and
a capacitance compensation circuit including a replica input capacitance, the capacitance compensation circuit configured to:
couple, during an input phase of the conversion process, a reference voltage or a ground to the replica input capacitance based on the value of the active bit, and
couple, during the redistribution phase of the conversion process, the replica input capacitance to the input capacitance to adjust the redistribution voltage.

2. The two-capacitor digital-to-analog converter circuit according to claim 1 , further including:
the first set of input switches are configured to, during an input phase of the conversion process in the first mode, to couple a first capacitor to a reference voltage or a ground based on the value of the active bit; and
the second set of input switches are configured to, during the input phase of the conversion process in the second mode, couple a second capacitor to the reference voltage or the ground based on the value of the active bit.

3. The two-capacitor digital-to-analog converter circuit according to claim 1 , further including:
an output switch configured to, during an output phase of the conversion process, couple the output voltage to an output of the two-capacitor digital-to-analog converter circuit.

4. The two-capacitor digital-to-analog converter circuit according to claim 1 , wherein the replica input capacitance is coupled to the input capacitance to adjust the redistribution voltage in order to reduce an effect of the input capacitance on the output voltage.

5. The two-capacitor digital-to-analog converter circuit according to claim 1 , wherein the capacitance compensation circuit includes:
a first compensation-input switch configured to couple, during the input phase of the conversion process in the first mode or the second mode, the replica input capacitance to a reference voltage when the value of the active bit is a one; and
a second compensation-input switch configure to couple, during the input phase of the conversion process in the first mode or the second mode, the replica input capacitance to a ground when the value of the active bit is a zero.

6. The two-capacitor digital-to-analog converter circuit according to claim 5 , wherein the capacitance compensation circuit includes:
a first compensation switch configured to, during the redistribution phase of the conversion process in the first mode, couple the replica input capacitance to a positive terminal of the first capacitor; and
a second compensation switch configured to, during the redistribution phase of the conversion process in the second mode, couple the replica input capacitance to a positive terminal of the second capacitor.

7. The two-capacitor digital-to-analog converter circuit according to claim 6 , further including:
a first capacitor coupling switch configured to, during the input phase of the conversion process in the second mode, couple the positive terminal of the first capacitor to the input capacitance at the input of the buffer amp; and
a second capacitor coupling switch configured to, during the input phase of the conversion process in the first mode, couple the positive terminal of the second capacitor to the input capacitance at the input of the buffer amp.

8. The two-capacitor digital-to-analog converter circuit according to claim 1 , wherein the buffer amp is an operational amplifier, the input capacitance at an input of the operational amplifier.

9. The two-capacitor digital-to-analog converter circuit according to claim 8 , wherein capacitance compensation circuit includes a transistor configured to replicate the input capacitance of the operational amplifier.

10. The two-capacitor digital-to-analog converter circuit according to claim 8 , wherein the operational amplifier is configured for unity gain and rail-to-rail operation.

11. The two-capacitor digital-to-analog converter circuit according to claim 1 , further comprising a sample-and-hold capacitor coupled to an output of the buffer amp.

12. The two-capacitor digital-to-analog converter circuit according to claim 11 , further comprising a first reset switch configured to discharge the first capacitor after the conversion process, a second reset switched configured to discharge the second capacitor after the conversion process, and a sample-and-hold reset switch configured to discharge the sample-and-hold capacitor after the conversion process.

13. A method for digital-to-analog conversion, the method comprising:
selecting a mode condition for an active bit of a digital word;
determining a first mode or a second mode for the active bit based on a value of the active bit and the selected mode condition;
executing an input phase to charge or discharge an averaging circuit including a first capacitor directly coupled between a first terminal of a redistribution switch and a ground and a second capacitor directly coupled between a second terminal of the redistribution switch and the ground, the input phase including:
in a first mode, charging or discharging the first capacitor and a replica input capacitance according the value of the active bit, and
in a second mode, charging or discharging the second capacitor and the replica input capacitance according to the value of the active bit; and

executing an average phase, the average phase including:
controlling the redistribution switch to couple the first capacitor and the second capacitor together to generate an average voltage for the active bit,
coupling the average voltage to a buffer amp having an input capacitance, and
coupling the replica input capacitance and the input capacitance together to generate an adjusted average voltage for the active bit at an input of the buffer amp.

14. The method for digital-to-analog conversion according to claim 13 , further comprising:
repeating the selecting, the determining, the executing the input phase, and executing the average phase to obtain an adjusted average voltage for each bit of the digital word in a sequence.

15. The method for digital-to-analog conversion according to claim 14 , further comprising:
outputting, from the buffer amp, the adjusted average voltage for a final bit of the digital word in the sequence as an output voltage, the output voltage corresponding to an analog conversion of the digital word.

16. The method for digital-to-analog conversion according to claim 15 , further com

Assignees

• Semiconductor Components Ind Llc

Inventors

• Ahmed Abdullah
• Onishi Akinobu
• Kawai Taichiro

Classifications

• H03M1/667

  Recirculation type · CPC title

• H03M1/1014 Primary

  at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/804 Primary

  with charge redistribution · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title