ESD protection circuit for I/O buffer

Patent metadata

Field	Value
Publication number	US-11431165-B2
Application number	US-202016999958-A
Country	US
Kind code	B2
Filing date	Aug 21, 2020
Priority date	Mar 4, 2020
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

An ESD protection circuit for an input/output buffer in which when an ESD pulse or event occurs, an ESD surge on a pad is discharged to a diode and a transistor channel, thereby enhancing the efficiency of the ESD protection circuit. The ESD protection circuit includes a floating N-well bias circuit connected to a pad at an output of driver circuit and outputting a bias voltage based on or in response to a supply voltage; a switch circuit connected to a logic circuit and the driver circuit, and configured to connect and disconnect the logic circuit and the driver circuit based on or in response to the supply voltage; and a pull-down circuit connected to the driver circuit, configured to output a voltage to the driver circuit based on or in response to the supply voltage.

First claim

What is claimed is:

1. An ESD protection circuit for an input/output buffer including a logic circuit and a driver circuit, the ESD protection circuit comprising:
a floating N-well bias circuit connected to a pad at an output of the driver circuit, the floating N-well bias circuit having an output voltage based on or in response to a supply voltage;
a switch circuit connected to a pulldown node that connects the logic circuit and the driver circuit, the switch circuit configured to switch a connection between the logic circuit and the driver circuit based on or in response to the supply voltage; and
a pull-down circuit connected to a pullup node that connects the logic circuit and the driver circuit, the pull-down circuit outputting a voltage to the driver circuit based on or in response to the supply voltage,
wherein the floating N-well bias circuit comprises one or more PMOS transistors and an NMOS transistor,
the switch circuit is connected to the pulldown node in series, and comprises a PMOS transistor and an NMOS transistor, and
the pull-down circuit is connected to the pullup node in parallel.

2. The ESD protection circuit of claim 1 , wherein the output voltage of the floating N-well bias circuit is a floating N-well bias voltage, and
the floating N-well bias circuit is configured to output the supply voltage as the floating N-well bias voltage during normal operation.

3. The ESD protection circuit of claim 1 , wherein the output voltage of the floating N-well bias circuit is a floating N-well bias voltage, and
the floating N-well bias circuit is configured to output a voltage on the pad as the floating N-well bias voltage when the supply voltage is at or near a ground potential.

4. The ESD protection circuit of claim 1 , wherein the switch circuit connects the logic circuit and the pulldown node to the driver circuit when the supply voltage is in a normal range.

5. The ESD protection circuit of claim 1 , wherein the switch circuit disconnects the logic circuit and the pulldown node when an ESD pulse or event occurs.

6. The ESD protection circuit of claim 1 , wherein the pull-down circuit operates in a sleep mode when the supply voltage is in a normal range.

7. The ESD protection circuit of claim 1 , wherein the pull-down circuit outputs a ground potential or a voltage of 0 V to the pullup node when an ESD pulse or event occurs.

Assignees

• Db Hitek Co Ltd

Inventors

• Lee Sang-Mok
• Jang Joon-Tae
• Kim Seung-Hoo
• Cha Jae-Ah

Classifications

• H02H9/045 Primary

  adapted to a particular application and not provided for elsewhere · CPC title

• H03K19/0136

  by means of a pull-up or down element · CPC title

• H02H9/046

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H03K17/08104 Primary

  in field-effect transistor switches (H03K17/0812, H03K17/0814 take precedence) · CPC title

• H10D89/811 Primary

  using FETs as protective elements · CPC title