LED chip, LED light emitting substrate, display device and control method thereof

US11430913B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11430913-B2
Application numberUS-201716063336-A
CountryUS
Kind codeB2
Filing dateDec 7, 2017
Priority dateApr 12, 2017
Publication dateAug 30, 2022
Grant dateAug 30, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure relates to the field of LED display technologies, and provides an LED chip, an LED light emitting substrate, a display device and a control method thereof. Specifically, the LED chip comprises: an N-type semiconductor layer, a P-type semiconductor layer, as well as a quantum well layer between the N-type semiconductor layer and the P-type semiconductor layer. The quantum well layer is made of indium gallium nitride, wherein indium atoms have a molar ratio of greater than or equal to 0.3 in the indium gallium nitride.

First claim

Opening claim text (preview).

The invention claimed is: 1. A display device, comprising: a LED light emitting substrate, and an array of pixel units, each pixel unit comprising a plurality of sub-pixel units, wherein the LED light emitting substrate comprises a plurality of LED chips and a circuit board, wherein the LED chips comprises an N-type semiconductor layer, a quantum well layer and a P-type semiconductor layer, the quantum well layer is located between the N-type semiconductor layer and the P-type semiconductor layer, and the quantum well layer is made of indium gallium nitride, wherein indium atoms have a molar ration of greater than or equal to 0.3 in the indium gallium nitride, the LED chips are arranged on the circuit board, and the circuit board comprises a base substrate and a drive circuit arranged on the base substrate for driving the LED chips, each LED chip of the LED light emitting substrate is located within a sub-pixel unit, and the drive circuit of the LED light emitting substrate is configured to transfer current to each LED chip such that the LED chip emits light of a corresponding wavelength. 2. The display device according to claim 1 , wherein each pixel unit at least comprises a blue sub-pixel unit, and a blue filter layer is further arranged on a light exit side of the LED chip corresponding to each blue sub-pixel unit. 3. The display device according to claim 2 , wherein each pixel unit further comprises a red sub-pixel unit and a green sub-pixel unit, and a red filter layer is further arranged on a light exit side of the LED chip corresponding to each red sub-pixel unit, and a green filter layer is further arranged on a light exit side of the LED chip corresponding to each green sub-pixel unit. 4. The display device according to claim 2 , further comprises: a lower polarizing unit, a liquid crystal layer and an upper polarizing unit arranged sequentially in a light exit direction of the LED light emitting substrate, wherein a transmission axis direction of the lower polarizing unit is perpendicular to or in parallel with a transmission axis direction of the upper polarizing unit. 5. The display device according to claim 4 , wherein at least one of the lower polarizing unit and the upper polarizing unit comprises a metal wire grating. 6. The display device according to claim 5 , wherein the lower polarizing unit comprises a metal wire grating, and the metal wire grating is arranged on a light exit side of each LED chip. 7. A method for controlling a display device to achieve color display, wherein the display device comprises: a LED light emitting substrate, and an array of pixel units, each pixel unit comprising a blue sub-pixel unit, a green sub-pixel unit and a red sub-pixel unit, wherein the LED light emitting substrate comprises a plurality of LED chips and a circuit board, wherein the LED chips comprises an N-type semiconductor layer, a quantum well layer and a P-type semiconductor layer, the quantum well layer is located between the N-type semiconductor layer and the P-type semiconductor layer, and the quantum well layer is made of indium gallium nitride, wherein indium atoms have a molar ratio of greater than or equal to 0.3 in the indium gallium nitride, the LED chips are arranged on the circuit board, and the circuit board comprises a base substrate and a drive circuit arranged on the base substrate for driving the LED chips, each LED chip of the LED light emitting substrate is located within a corresponding sub-pixel unit, wherein the drive circuit of the LED light emitting substrate is configured to transfer current to each LED chip such that the LED chip emits light of a corresponding wavelength, and the method comprising: inputting a first current into the LED chip disposed within the red sub-pixel unit; inputting a second current into the LED chip disposed within the green sub-pixel unit; and inputting a third current into the LED chip disposed within the blue sub-pixel unit, wherein a current value of the third current is larger than a current value of the first current, but smaller than a current value of the second current. 8. The method according to claim 7 , wherein the current value of the first current is 0.1 mA, the current value of the second current is 60 mA, and the current value of the third current is 8 mA. 9. The method according to claim 8 , wherein a ratio of duty cycles of the first current, the second current and the third current is 120:1:4. 10. The method according to claim 7 , wherein the display device further comprises a blue filter layer, a red filter layer and a green filter layer arranged respectively on light exit sides of the LED chips corresponding to each blue sub-pixel unit, each green sub-pixel unit and each red sub-pixel unit. 11. The method according to claim 7 , wherein the current value of the first current falls in a range of smaller than 0.1 mA the current value of the second current falls in a range of 25 mA-100 mA; and the current value of the third current falls in a range of greater than 0.5 mA. 12. The method according to claim 7 , wherein a duty cycle of the third current is larger than a duty cycle of the second current, but smaller than a duty cycle of the first current. 13. A display device, comprising: a LED light emitting substrate, and an array of pixel units, each pixel unit comprising a plurality of sub-pixel units, wherein the LED light emitting substrate comprises a plurality of LED chips and a circuit board, wherein the LED chips comprises an N-type semiconductor layer, a quantum well layer and a P-type semiconductor layer, the quantum well layer is located between the N-type semiconductor layer and the P-type semiconductor layer, and the quantum well layer is made of indium gallium nitride, wherein indium atoms have a molar ratio of greater than or equal to 0.3 in the indium gallium nitride, the LED chips are arranged on the circuit board, the circuit board comprises a base substrate and a drive circuit arranged on the base substrate for driving the LED chips, and the circuit board comprises a CMOS substrate or a TFT substrate, each LED chip of the LED light emitting substrate is located within a sub-pixel unit, and the drive circuit of the LED light emitting substrate is configured to transfer current to each LED chip such that the LED chip emits light of a corresponding wavelength.

Assignees

Inventors

Classifications

  • Package configurations · CPC title

  • Layout of electrodes and connections · CPC title

  • Wire-grid polarisers · CPC title

  • the different display panel areas being distributed in two dimensions, e.g. matrix · CPC title

  • Details of control of colour illumination sources · CPC title

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What does patent US11430913B2 cover?
The present disclosure relates to the field of LED display technologies, and provides an LED chip, an LED light emitting substrate, a display device and a control method thereof. Specifically, the LED chip comprises: an N-type semiconductor layer, a P-type semiconductor layer, as well as a quantum well layer between the N-type semiconductor layer and the P-type semiconductor layer. The quantum …
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Beijing Boe Display Tech Co
What technology area does this patent fall under?
Primary CPC classification G09G3/3225. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 30 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).