Method for manufacturing transistor

Patent metadata

Field	Value
Publication number	US-11430875-B2
Application number	US-201916981603-A
Country	US
Kind code	B2
Filing date	Mar 27, 2019
Priority date	Apr 5, 2018
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A first barrier layer, a channel layer, a second barrier layer, and a first bonding layer made of high-resistance AlGaN doped with Fe are formed on a first substrate. Thereafter, the first substrate and the second substrate are pasted in a state where the first bonding layer and a second bonding layer made of high-resistance GaN doped with Fe are opposed to each other.

First claim

The invention claimed is:

1. A method of manufacturing a transistor comprising:
forming a buffer layer of a nitride semiconductor on a first substrate;
forming a first material stack, wherein forming the first material stack comprises crystal-growing a first barrier layer, a channel layer, a second barrier layer, and a first bonding layer on the buffer layer in this order, and wherein a principal surface of the first material stack is a group III polarity surface, the first bonding layer comprises the nitride semiconductor;
forming a second bonding layer on a second substrate, the second bonding layer comprises the nitride semiconductor;
pasting the first substrate to the second substrate such that the first bonding layer faces the second bonding layer; and
at least partially removing the buffer layer and the first substrate to form a second material stack, the second material stack comprises the second barrier layer, the channel layer, and the first barrier layer on the second substrate in this order, and wherein a principal surface of the second material stack is a group V polarity surface, wherein after removing the first substrate, a transistor is formed by the second barrier layer, the channel layer, and the first barrier layer on the second substrate.

2. The method of manufacturing a transistor according to claim 1 , wherein the channel layer is made of a material having a bandgap smaller than a bandgap of the first barrier layer and a bandgap of the second barrier layer.

3. The method of manufacturing a transistor according to claim 1 , wherein the channel layer comprises GaN, InGaN, AlGaN, or InN.

4. The method of manufacturing a transistor according to claim 1 , wherein the first barrier layer comprises AlGaN, InAlN, InAIGaN, AlN, or GaN.

5. The method of manufacturing a transistor according to claim 1 , wherein the second barrier layer comprises AlGaN, InAlN, InAIGaN, AlN, or GaN.

6. The method of manufacturing a transistor according to claim 1 , wherein the first bonding layer or the second bonding layer is doped with C, Fe, Zn, or Mg.

7. The method of manufacturing a transistor according to claim 1 , wherein the first bonding layer or the second bonding layer is increased in resistance or converted into a p type.

8. A method of manufacturing a transistor comprising:
forming a buffer layer made of a nitride semiconductor on a first substrate;
forming a first material stack, wherein forming the first material stack comprises crystal-growing a first barrier layer, a channel layer, a second barrier layer, and a first bonding layer on the buffer layer in this order, and wherein a principal surface of the first material stack is a group III polarity surface, the first bonding layer comprises the nitride semiconductor;
pasting the first substrate to a second substrate such that the first bonding layer and a surface of the second substrate face each other; and
at least partially removing the buffer layer and the first substrate to form a second material stack, the second material stack comprising the second barrier layer, the channel layer, and the first barrier layer on the second substrate in this order, wherein a principal surface of the second material stack is a group V polarity surface;
wherein after removing the first substrate, a transistor is formed by the second barrier layer, the channel layer, and the first barrier layer on the second substrate;
wherein the channel layer has a bandgap smaller than a bandgap of the first barrier layer and a bandgap of the second barrier layer;
wherein the channel layer is made of GaN, InGaN, AlGaN, or InN;
wherein the first barrier layer is made of AlGaN, InAlN, InAlGaN, AlN, or GaN;
wherein the second barrier layer is made of AlGaN, InAlN, InAlGaN, AlN, or GaN;
wherein the first bonding layer is doped with C, Fe, Zn, or Mg; and
wherein the first bonding layer is increased in resistance or converted into a p type.

9. The method of manufacturing a transistor according to claim 8 , further comprising:
forming a second bonding layer made of the nitride semiconductor on the second substrate before pasting the first substrate and the second substrate, wherein the first substrate and the second substrate are pasted in a state where the first bonding layer and the second bonding layer face each other.

10. The method of manufacturing a transistor according to claim 9 , wherein the second bonding layer is made of the nitride semiconductor and is doped with C, Fe, Zn, or Mg, and wherein the second bonding layer is increased in resistance or converted into a p type.

11. A method of manufacturing a transistor comprising:
forming a buffer layer of a nitride semiconductor on a first substrate;
forming a first material stack, wherein forming the first material stack comprises crystal-growing a first barrier layer, a channel layer, a second barrier layer, and a first bonding layer on the buffer layer in this order, and wherein a principal surface of the first material stack is a group III polarity surface, the first bonding layer comprises the nitride semiconductor;
forming a second bonding layer on a second substrate, the second bonding layer comprises the nitride semiconductor;
pasting the first substrate to the second substrate such that the first bonding layer faces the second bonding layer; and
at least partially removing the buffer layer and the first substrate to form a second material stack, the second material stack comprises the second barrier layer, the channel layer, and the first barrier layer on the second substrate in this order, and wherein a principal surface of the second material stack is a group V polarity surface;
wherein after removing the first substrate, a transistor is formed by the second barrier layer, the channel layer, and the first barrier layer on the second substrate;
wherein the channel layer is made of a material having a bandgap smaller than a bandgap of the first barrier layer and a bandgap of the second barrier layer;
wherein the channel layer comprises GaN, InGaN, AlGaN, or InN;
wherein the first barrier layer comprises AlGaN, InAlN, InAIGaN, AlN, or GaN;
wherein the second barrier layer comprises AlGaN, InAlN, InAIGaN, AlN, or GaN;
wherein the first bonding layer or the second bonding layer is doped with C, Fe, Zn, or Mg; and
wherein the first bonding layer or the second bonding layer is increased in resistance or converted into a p type.

Assignees

• Nippon Telegraph & Telephone

Inventors

• Hoshi Takuya
• Yoshiya Yuki
• Sugiyama Hiroki
• Matsuzaki Hideaki

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title

• H10D30/015 Primary

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title