Crystalline semiconductor and oxide semiconductor thin-film transistor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11430847-B2
Application number	US-202016820102-A
Country	US
Kind code	B2
Filing date	Mar 16, 2020
Priority date	Aug 30, 2016
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A method of manufacturing a semiconductor device. A pre first semiconductor pattern having a crystalline semiconductor material is formed on a base substrate. A pre first insulation layer is formed on the pre first semiconductor pattern. A first semiconductor pattern is formed by defining a channel region in the pre first semiconductor pattern. A pre protection layer is formed on the pre first insulation layer. A pre second semiconductor pattern including an oxide semiconductor material is formed on the pre protection layer. A pre second insulation layer is formed on the pre second semiconductor pattern. The pre second insulation layer is patterned using an etching gas such that at least a portion of the pre second semiconductor pattern is exposed. A second semiconductor pattern is formed by defining a channel region in the pre second semiconductor pattern. The pre protection layer has a material with a first etch selectivity that is different from a second etch selectivity of the second insulation layer with respect to the etching gas.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a base substrate;
a first transistor disposed on the base substrate, the first transistor comprising a first control electrode, and a first semiconductor pattern that includes a crystalline semiconductor,
a second transistor disposed on the base substrate, the second transistor comprising a second control electrode, and a second semiconductor pattern that includes an oxide semiconductor;
a first insulation layer disposed above the base substrate;
a protection layer disposed above the first insulation layer;
a second insulation layer disposed above the protection layer and between the second semiconductor pattern and the second control electrode;
a first capacitor electrode disposed above the first insulation layer and below the protection layer;
a second capacitor electrode disposed above the first capacitor electrode and the protection layer; and
a third insulation layer disposed directly on upper surfaces of the protection laver, and on side surfaces of the second capacitor electrode and the second insulation layer,
wherein the second semiconductor pattern and the second control electrode are disposed above the protection layer, and the first control electrode is covered by the protection layer.

2. The semiconductor device of claim 1 ,
wherein the protection layer is disposed between the first semiconductor pattern and the second semiconductor pattern and that includes a metal oxide,
wherein the protection layer comprises a material having a first etch selectivity that is different from a second etch selectivity of the second insulation layer, and wherein
the first insulation layer is disposed between the first semiconductor pattern and the first control electrode.

3. The semiconductor device of claim 1 ,
wherein the second semiconductor pattern is disposed above the protection layer, the second control electrode is disposed above the second semiconductor pattern, and
wherein the first semiconductor pattern and the second semiconductor pattern are disposed on different layers with the protection layer therebetween.

4. The semiconductor device of claim 1 , wherein the protection layer is disposed above the first control electrode.

Assignees

• Samsung Display Co Ltd

Inventors

• SON Kyoungseok
• Kim Jaybum
• Kim Eoksu
• LIM Junhyung
• Lim Jihun

Classifications

• H10P50/282

  of inorganic materials · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title