Method for preparing interlayer insulating layer and method for manufacturing thin film transistor, thin film transistor

Patent metadata

Field	Value
Publication number	US-11430816-B2
Application number	US-202016862865-A
Country	US
Kind code	B2
Filing date	Apr 30, 2020
Priority date	Aug 8, 2019
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

The present disclosure provides a method for preparing an interlayer insulating layer and a method for manufacturing a thin film transistor, and a thin film transistor, belongs to the field of display technology, and can solve the problem of poor resistance to breakdown of the interlayer insulating layer in the related art. The method for preparing an interlayer insulating layer includes the following steps: forming a silicon oxide layer with a first reaction gas and forming a silicon nitride layer with a second reaction gas such that hydrogen content in the silicon nitride layer is less than or equal to hydrogen content in the silicon oxide layer.

First claim

What is claimed is:

1. A method for manufacturing a thin film transistor in an OLED display product, comprising:
forming a metal oxide semiconductor layer on a substrate and performing a patterning process on the metal oxide semiconductor layer to form a metal oxide semiconductor active layer, such that the metal oxide semiconductor active layer comprises a source contact region in contact with a source electrode of the thin film transistor and a drain contact region in contact with a drain electrode of the thin film transistor;
forming a gate insulating layer and a gate electrode on the substrate, such that the gate insulating layer and the gate electrode only cover the metal oxide semiconductor active layer and expose the source contact region and the drain contact region of the metal oxide semiconductor active layer;
forming an interlayer insulating layer on the substrate to cover an exposed part of the substrate, an exposed part of the metal oxide semiconductor active layer, and an exposed part of the gate electrode, wherein an upper surface, above the gate electrode, of the interlayer insulating layer, is a flat surface;
forming a source contact hole and a drain contact hole, at positions respectively corresponding to the source contact region and the drain contact region of the metal oxide semiconductor active layer, such that the source contact hole and the drain contact hole extend through the interlayer insulating layer, a sidewall of the source contact hole and a sidewall of the drain contact hole are respectively adjacent to the gate electrode and are spaced apart from the gate electrode by the interlayer insulating layer; and
forming a metal layer on the interlayer insulating layer ad performing a patterning process on the metal layer to form a source electrode and a drain electrode, such that the source electrode and the drain electrode respectively extend through the source contact hole and the drain contact hole, and are respectively formed as layers covering a part of the metal oxide semiconductor active layer and respective inner sidewalls of the source contact hole and the drain contact hole according to shapes of respective inner surface shape of the source contact hole and the drain contact hole,
wherein forming the interlayer insulating layer comprises:
depositing methylsilane and nitrous oxide to form a silicon oxide layer, sucha that the silicon oxide layer covers the source contact region and drain contact region of the metal oxide semiconductor active layer and the gate electrode, and the hydrogen content in the silicon oxide layer is 1% to 2%;
depositing trisilylamine and nitrogen to form a silicon nitride layer on the silicon oxide layer, such that the silicon nitride layer covers the silicon oxide layer, the hydrogen content in the silicon nitride layer is 1% to 2%, and a refractive index of the silicon nitride layer is in a range between 2.0 and 2.1; and
hydrogen content in the silicon nitride film layer is less than or equal to hydrogen content in the silicon oxide film layer.

2. The method for manufacturing a thin film transistor according to claim 1 , wherein the silicon nitride layer has a dielectric constant higher than that of the silicon oxide layer.

3. The method for manufacturing a thin film transistor according to claim 2 , wherein the silicon oxide layer has a thickness of more than 2500 angstroms, and the silicon nitride layer has a thickness of more than 2500 angstroms.

4. The method for manufacturing a thin film transistor according to claim 1 , wherein the hydrogen content in the silicon oxide layer is 1.9%; and the hydrogen content in the silicon nitride layer is 1.8.

5. A thin film transistor, comprising:
a metal oxide semiconductor active layer on a substrate, wherein the metal oxide semiconductor active layer comprises a source contact region in contact with a source electrode of the thin film transistor and a drain contact region in contact with a drain electrode of the thin film transistor;
a gate insulating layer and a gate on the substrate, wherein the gate insulating layer and the gate electrode only cover the metal oxide semiconductor active layer and expose the source contact region and the drain contact region of the metal oxide semicoductor active layer;
an interlayer insulating layer, wherein the interlayer insulating layer covers an exposed part of the substrate, an exposed part of the metal oxide semiconductor active layer, and an exposed part of the gate electrode; an upper surface, above the gate electrode, of the interlayer insulating layer, is a flat surface; the interlayer insulating layer further comprises a source contact hole and a drain contact hole, at positions respectively corresponding to the source contact region and the drain contact region of the metal oxide semiconductor active layer, extending through the interlayer insulating layer; and a sidewall of the source contact hole and a sidewall of the drain contact hole are respectively adjacent to the gate electrode and are spaced apart from the gate electrode by the interlayer insulating layer;
a source electrode and a drain electrode, wherein the source electrode and the drain electrode respectively extend through the source contact hole and the drain contact hole, and are respectively formed as layers covering a part of the metal oxide semiconductor active layer and respectively inner sidewalls of the source contact hole and the drain contact hole according to shapes of respectively inner surface shape of the source contact hole and the drain contact hole,
wherein the interlayer insulating layer comprises:
a siliconoxide layer formed by depositing methylsilane and nitrous oxide, wherein the silicon oxide layer overs the source contact region and drain contact region of the metal oxide semiconductor active layer and the gate electrode, and the hydrogen conteact in the silicon oxide layer is 1% to 2%;
a silicon nitride layer formed by depositing trisilylamine and nitrogen on the silicon oxide layer, wherein the silicon nitride layer covers the silicon oxide layer, the hydrogen content in the silicon nitride layer is 1% to 2%, and a refractive index of the silicon nitride layer is in a range between 2.0 and 2.1; and
hydrogen content in the silicon nitride film layer is less than or equal to hydrogen content in the silicon oxide film layer.

6. The thin film transistor according to claim 5 , wherein the silicon oxide layer has a thickness of more than 2500 angstroms, and the silicon nitride layer has a thickness of more than 2500 angstroms.

7. The thin film transistor according to claim 5 , wherein the silicon nitride layer has a dielectric constant higher than that of the silicon oxide layer.

8. The thin film transistor according to claim 5 , wherein the hydrogen content in the silicon oxide layer is 1.9%; and the hydrogen content in the silicon nitride layer is 1.8.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Ming
• Zhao Ce
• Song Wei

Classifications

• H10P14/69433 Primary

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6682

  the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title