TVS device and manufacturing method therefor

Patent metadata

Field	Value
Publication number	US-11430780-B2
Application number	US-201917266134-A
Country	US
Kind code	B2
Filing date	Nov 1, 2019
Priority date	Nov 6, 2018
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A TVS device and a manufacturing method therefor. The TVS device comprises: a first doping type semiconductor substrate (100); a second doping type deep well I (101), a second doping type deep well II (102), and a first doping type deep well (103) provided on the semiconductor substrate; a second doping type heavily doped region I (104) provided in the second doping type deep well I (101); a first doping type well region (105) and a first doping type heavily doped region I (106) provided in the second doping type deep well II (102); a first doping type heavily doped region II (107) and a second doping type heavily doped region II (108) provided in the first doping type deep well (105); a second doping type heavily doped region III (109) located in the first doping type well region (105) and the second doping type deep well II (102); and a first doping type doped region (110) provided in the first doping type well region (105).

First claim

What is claimed is:

1. A Transient Voltage Suppressor (TVS) device, comprising:
a first-doping-type semiconductor substrate;
a first second-doping-type deep well and a second second-doping-type deep well disposed on the first-doping-type semiconductor substrate, and a first-doping-type deep well located between the first second-doping-type deep well and the second second-doping-type deep well;
a first second-doping-type heavily doped region disposed in the first second-doping-type deep well;
a first-doping-type well region and a first first-doping-type heavily doped region disposed in the second second-doping-type deep well;
a second first-doping-type heavily doped region and a second second-doping-type heavily doped region disposed in the first-doping-type well region;
a third second-doping-type heavily doped region partially located in the first-doping-type well region and partially located in the second second-doping-type deep well; and
a first-doping-type doped region disposed in the first-doping-type well region and in contact with the third second-doping-type heavily doped region;
wherein, the first-doping-type and the second-doping-type are opposite.

2. The TVS device according to claim 1 , wherein the first second-doping-type heavily doped region and the first first-doping-type heavily doped region are connected to an input/output terminal, and the second first-doping-type heavily doped region and the second second-doping-type heavily doped region are connected to a ground terminal.

3. The TVS device according to claim 1 , wherein the first first-doping-type heavily doped region, the second second-doping-type deep well, the third second-doping-type heavily doped region, the first-doping-type well region, and the second first-doping-type heavily doped region constitute a first triode;
the third second-doping-type heavily doped region and the first-doping-type doped region constitute a Zener diode;
the third second-doping-type heavily doped region, the first-doping-type well region, and the second second-doping-type heavily doped region constitute a second triode;
the first second-doping-type heavily doped region, the first second-doping-type deep well, the first-doping-type deep well, and the second second-doping-type deep well constitute a third triode;
the second first-doping-type heavily doped region, the first-doping-type well region, the second second-doping-type deep well, and the first-doping-type deep well constitute a fourth triode; and
the first-doping-type well region and the second first-doping-type heavily doped region constitute a resistor.

4. The TVS device according to claim 3 , wherein when a positive instantaneous pulse signal enters from an input/output terminal, the fourth triode and the third triode constitute a first thyristor, and a trigger voltage of the first thyristor is higher than a breakdown voltage of the Zener diode.

5. The TVS device according to claim 3 , wherein when a negative instantaneous pulse signal enters from the input/output terminal, the third triode and the fourth triode constitute a second thyristor, and a trigger voltage of the second thyristor is less than a reverse biased breakdown voltage of the first triode.

6. The TVS device according to claim 4 , wherein the breakdown voltage of the Zener diode is 6 V to 8 V.

7. The TVS device according to claim 1 , wherein the first-doping-type doped region is located below the third second-doping-type heavily doped region.

8. The TVS device according to claim 1 , wherein doping ions of the first second-doping-type heavily doped region comprises arsenic ions and phosphorus ions, and a doping concentration of the arsenic ions is 5E15 cm −3 to 1E16 cm −3 , and a doping concentration of the phosphorus ions is 1E14 cm −3 to 1E15 cm −3 .

9. The TVS device according to claim 1 , wherein doping ions of the first-doping-type doped region comprises phosphorus ions and boron ions, and a doping concentration of the phosphorus ions is 1E13 cm −3 to 1E14 cm −3 , and a doping concentration of the boron ions is 1E14 cm −3 to 1E15 cm −3 .

10. The TVS device according to claim 1 , wherein a doping concentration of the first-doping-type well region is 1E13 cm −3 to 1E14 cm −3 , and a doping concentration of doping ions of the first first-doping-type heavily doped region is 1E15 cm −3 to 1E16 cm −3 .

11. The TVS device according to claim 1 , wherein the first-doping-type is P type and the second-doping-type is N type.

12. A manufacturing method for a TVS device, comprising:
providing a first-doping-type semiconductor substrate;
performing ion implantation to form a first second-doping-type ion implantation region, a second second-doping-type ion implantation region, and a first first-doping-type ion implantation region located between the first second-doping-type ion implantation region and the second second-doping-type ion implantation region on the first-doping-type semiconductor substrate;
performing a high-temperature drive-in process to form a first second-doping-type deep well, a second second-doping-type deep well, and a first-doping-type deep well located between the first second-doping-type deep well and the second second-doping-type deep well;
forming a first-doping-type well region in the second second-doping-type deep well;
performing ion implantation to form a first second-doping-type heavily doped region located in the first second-doping-type deep well, a second second-doping-type heavily doped region located in the first-doping-type well region, a third second-doping-type heavily doped region partially located in the first-doping-type well region and partially located in the second second-doping-type deep well, and a first first-doping-type heavily doped region located in the second second-doping-type deep well and a second first-doping-type heavily doped region located in the first-doping-type well region; and
performing first-doping-type ion implantation to form a first-doping-type doped region in the first-doping-type well region, the first-doping-type doped region being in contact with the third second-doping-type heavily doped region.

13. The manufacturing method according to claim 12 , wherein a method of forming the first-doping-type well region comprises:
performing ion implantation to form a second first-doping-type ion implanted region in the second second-doping-type deep well; and
performing a high-temperature drive-in process to form the first-doping-type well region.

14. The manufacturing method according to claim 12 , wherein after the step of forming the first-doping-type doped region, the manufacturing method further comprises:
performing an annealing process to activate doping ions.

15. The manufacturing method according to claim 12 , wherein the step of forming the first second-doping-type ion implanted region, the second second-doping-type ion implanted region, and the first first-doping-type ion implanted region comprises:
forming a first mask layer covering the semiconductor substrate;
etching the first mask layer to form a second-doping-type implantation window;
performing second-doping-type ion implantation to form the first second-doping-type ion implanted region and the second second-doping-type ion implanted region;
forming a second mask layer covering the first second-doping-type ion implanted region and the second second-doping-type ion implanted region, and removing the first mask layer; and
performing first-doping-type ion implantation using the second mask layer as a mask to form the first first-doping-type ion implanted region.

Assignees

• Csmc Technologies Fab2 Co Ltd

Inventors

• Cheng Shikang
• Gu Yan
• Zhang Sen

Classifications

• H10P30/22

  using masks · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/1404

  using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase · CPC title

• H10D84/135

  the built-in components being diodes · CPC title

• H10D62/103 Primary

  for increasing or controlling the breakdown voltage of reverse-biased devices · CPC title