ESD protection in an electronic device

Patent metadata

Field	Value
Publication number	US-11430749-B2
Application number	US-201916662425-A
Country	US
Kind code	B2
Filing date	Oct 24, 2019
Priority date	Oct 31, 2018
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

According to one configuration, a fabricator produces an electronic device to include: a substrate; a transistor circuit disposed on the substrate; silicide material disposed on first regions of the transistor circuit; and the silicide material absent from second regions of the transistor circuit. Absence of the silicide material over the second regions of the respective of the transistor circuit increases a resistance of one or more parasitic paths (such as one or more parasitic transistors) in the transistor circuit. The increased resistance in the one or more parasitic paths provides better protection of the transistor circuit against electro-static discharge conditions.

First claim

We claim:

1. An apparatus comprising:
a high-ohmic substrate;
a first transistor circuit fabricated on the high-ohmic substrate;
a second transistor circuit fabricated on the high-ohmic substrate;
silicide material disposed on first regions of the first transistor circuit;
the silicide material being absent from second regions of the first transistor circuit;
the silicide material being absent from a third region of the apparatus between the first transistor circuit and the second transistor circuit;
wherein the absence of the silicide material from the region provides increased resistance of a parasitic path between the first transistor circuit and the second transistor circuit; and
wherein the parasitic path is a parasitic transistor path extending from the first transistor circuit to the second transistor circuit.

2. The apparatus as in claim 1 , wherein the second regions reside between drain regions and source regions of the first transistor circuit.

3. The apparatus as in claim 2 , wherein the first transistor circuit includes multiple transistors connected in parallel, the multiple transistors disposed on the high-ohmic substrate and being non-isolated transistors.

4. The apparatus as in claim 3 , wherein the parasitic path is first parasitic path; and
wherein absence of the silicide material over the second regions provides increased resistance of a second parasitic path in the first transistor circuit and wherein the second parasitic path in the first transistor circuit supports flow of current during exposure of the first transistor circuit to an ESD (Electro-Static Discharge) condition.

5. The apparatus as in claim 4 , wherein the second parasitic path in the first transistor circuity is a parasitic bipolar junction transistor.

6. The apparatus as in claim 4 , wherein the second parasitic path in the first transistor circuit extends between drain regions and source regions of the multiple transistors.

7. The apparatus as in claim 3 , wherein the silicide material is disposed over: i) drain regions of the multiple transistors in the first transistor circuit, and ii) source regions of the multiple transistors in the first transistor circuit;
wherein the silicide material is absent over a first strip of the first transistor circuit between the drain regions and the gate regions; and
wherein the silicide material is absent over a second strip of the first transistor circuit between the source regions and the gate regions.

8. The apparatus as in claim 1 , wherein
the silicide material is absent over a perimeter region of the first transistor circuit between the first transistor circuit and the second transistor circuit, the second transistor circuit being adjacent to the first transistor circuit.

9. The apparatus as in claim 1 , wherein the high-ohmic substrate has a resistance of more than 100 ohms×centimeter.

10. The apparatus as in claim 1 , wherein the first transistor circuit includes multiple transistors connected in parallel; and
wherein the multiple transistors of the first transistor circuit are controlled by a common gate.

11. The apparatus as in claim 10 , wherein the silicide material is absent from residing over the common gate.

12. The apparatus as in claim 1 , wherein the second regions include: i) a first strip of area disposed over a drain region of the first transistor circuit, the silicide material being absent from the first strip of area, and ii) a second strip of area disposed over a source region of the first transistor circuit, the silicide material being absent from the second strip of area.

13. The apparatus as in claim 12 , wherein the first strip of area is disposed between a gate node of the first transistor circuit and a sequence of multiple drain nodes of the first transistor circuit; and
wherein the second strip of area is disposed between the gate node of the first transistor circuit and a sequence of multiple source nodes of the first transistor circuit.

14. The apparatus as in claim 13 , wherein a width of the first strip of area is operative to control a resistance of a first parasitic path of the first transistor circuit; and
wherein a width of the second strip of area is operative to control a resistance of a second parasitic path of the first transistor circuit.

15. The apparatus as in claim 1 , wherein parasitic resistive paths of the first transistor circuit are controlled via dimensions of the second regions.

16. The apparatus as in claim 1 , wherein the first regions include: i) a first silicide region disposed over a drain region of the first transistor circuit including a sequence of drain nodes, the silicide material being present in the first silicide region, and ii) a second silicide region disposed over a source region of the first transistor circuit including a sequence of source nodes, the silicide material being present in the second silicide region.

17. The apparatus as in claim 16 , wherein the second regions include: i) a first silicide-free region disposed over the drain region of the first transistor circuit, the silicide material being absent over the first silicide-free region, and ii) a second silicide-free region disposed over the source region of the first transistor circuit, the silicide material being absent over the second silicide-free region.

18. An apparatus comprising:
a high-ohmic substrate;
a first transistor circuit fabricated on the high-ohmic substrate:
a second transistor circuit fabricated on the high-ohmic substrate;
silicide material disposed on first regions of the first transistor circuit;
the silicide material being absent from second regions of the first transistor circuit;
the silicide material being absent from a third region of the apparatus between the first transistor circuit and the second transistor circuit;
wherein the first transistor circuit includes first transistors, the apparatus further comprising:
the second transistor circuit comprising:
second transistors;
silicide material disposed on first regions of second, transistor circuit; and

the silicide material being absent over second regions of the second transistor circuit, absence of the silicide material over the second regions of the second transistor circuit providing increased resistance of a parasitic path in the second transistor circuit;
a circuit path extending between the first transistor circuit and the second transistor circuit, the circuit path connecting the first transistor circuit and the second transistor circuit in series; and
the silicide material being absent over a periphery region of the first transistor circuit, the perimeter region disposed adjacent to the second transistor circuit.

19. An apparatus comprising:
a first transistor circuit fabricated on a substrate;
a second transistor circuit fabricated on the substrate, the first transistor circuit electrically connected to the second transistor circuit;
silicide material disposed on the first transistor circuit and the second transistor circuit; and
the silicide material being absent over a periphery region of the first transistor circuit; and
wherein absence of the silicide material over the periphery region of the first transistor provides increased resistance of a parasitic path formed via a combination of the first transistor circuit and the second transistor circuit and wherein the parasitic path is a parasitic transistor path extending from the first transistor circuit to the second transistor circuit.

20. The apparatus as in claim 19 , whe

Assignees

• Infineon Technologies Ag

Inventors

• Mergens Markus
• Simbuerger Werner

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W42/60 Primary

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D30/0223 Primary

  having source and drain regions or source and drain extensions self-aligned to sides of the gate · CPC title