Data protection in a pre-operation system environment based on an embedded key of an embedded controller

US11429722B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11429722-B2
Application numberUS-201816479737-A
CountryUS
Kind codeB2
Filing dateJan 29, 2018
Priority dateJan 29, 2018
Publication dateAug 30, 2022
Grant dateAug 30, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An example system with a pre-OS (Operating System) environment, the pre-OS environment includes a private memory that is isolated from a processor of the system. The pre-OS environment also includes an embedded controller (EC) coupled to the private memory, where the EC includes an embedded key. The EC is to execute instructions to generate an encryption key based on the embedded key; generate a signature key; obtain data; produce an integrity-verification tag based on a hash of the obtained data, where the hash employs the signature key; encrypt the obtained data based on the encryption key; store the encrypted data in the private memory; and store the integrity-verification tag in the private memory in association with the stored encrypted data.

First claim

Opening claim text (preview).

What is claimed is: 1. A system with a pre-OS (Operating System) environment, the pre-OS environment comprises: a private memory that is isolated from a processor of the system; and an embedded controller (EC) coupled to the private memory, wherein the EC includes an embedded key; the EC to execute instructions to: generate an encryption key based on the embedded key; generate a signature key based on the embedded key; obtain data; produce an integrity-verification tag based on a hash of the obtained data, wherein the hash employs the signature key; encrypt the obtained data based on the encryption key; store the encrypted data in the private memory in a first memory block, wherein the private memory includes a solid-state non-volatile computer storage medium that employs NOR logic gates; store the integrity-verification tag in the private memory in association with the stored encrypted data, wherein the private memory includes data sets that are used by the EC during a system's initial boot sequence and hardware initialization, and wherein the EC compares a second integrity-verification tag with the integrity-verification tag when the EC reads the stored encrypted data for integrity verification; and store a subsequent encrypted data set in the first memory block, wherein any bit “1” of a first addressable location is changed to “0” to indicate alteration of the stored encrypted data. 2. The system of claim 1 , wherein the encrypted data stored in the private memory is accessible only to the EC. 3. The system of claim 1 , wherein the embedded key is inaccessible and unattainable outside of the EC. 4. The system of claim 1 , wherein the integrity-verification tag includes a hash message authentication code (HMAC) that is based upon a keyed cryptographic hash function. 5. The system of claim 4 , wherein the EC reads the HMAC based on the signature key. 6. A non-transitory machine-readable storage medium encoded with instructions executable by a processor of a system, the machine-readable storage medium comprising instructions to: generate an encryption key based upon an embedded key installed into an embedded controller (EC) of the system; generate a signature key based on the embedded key; obtain data; produce an integrity-verification tag based on a function of the obtained data, wherein the function employs the signature key; encrypt the obtained data based on the encryption key; store the encrypted data in memory in a first memory block, wherein the memory includes a solid-state non-volatile computer storage medium that employs NOR logic gates; store the integrity-verification tag in the memory in association with the stored encrypted data, wherein the memory includes data sets that are used by the EC during a system's initial boot sequence and hardware initialization, and wherein the EC compares a second integrity-verification tag with the integrity-verification tag when the EC reads the stored encrypted data for integrity verification; and store a subsequent encrypted data set in the first memory block, wherein any bit “1” of a first addressable location is changed to “0” to indicate alteration of the stored encrypted data. 7. The non-transitory machine-readable storage medium of claim 6 , wherein the encryption key is based upon a combination of an initialization vector and a randomly generated number, the randomly generated number being seeded from the embedded key. 8. The non-transitory machine-readable storage medium of claim 7 further comprising instructions to update the encryption key by incrementing the initialization vector used in a previous encryption of data. 9. The non-transitory machine-readable storage medium of claim 6 , wherein the embedded key is inaccessible and unattainable outside of the EC. 10. The non-transitory machine-readable storage medium of claim 6 , wherein the function is a keyed cryptographic hash function. 11. A non-transitory machine-readable storage medium encoded with instructions executable by an embedded controller (EC) of a pre-OS (Operating System) environment, the machine-readable storage medium comprising instructions to: generate an encryption key based upon an embedded key of the EC, wherein the embedded key is inaccessible and unattainable outside the EC; generate a signature key based on the embedded key; obtain data; produce an integrity-verification tag based on a hash of the obtained data, wherein the hash employs the signature key; encrypt the obtained data based on the encryption key; store the encrypted data in memory in a first memory block, wherein the memory includes a solid-state non-volatile computer storage medium that employs NOR logic gates; store the integrity-verification tag in the memory in association with the stored encrypted data, wherein the memory includes data sets that are used by the EC during a system's initial boot sequence and hardware initialization, and wherein the EC compares a second integrity-verification tag with the integrity-verification tag when the EC reads the stored encrypted data for integrity verification; and store a subsequent encrypted data set in the first memory block, wherein any bit “1” of a first addressable location is changed to “0” to indicate alteration of the stored encrypted data. 12. The non-transitory machine-readable storage medium of claim 11 , the machine-readable storage medium further comprising instructions to update an initialization vector used, at least in part, to generate another encryption key. 13. The non-transitory machine-readable storage medium of claim 11 , wherein the integrity-verification tag includes a hash message authentication code (HMAC) that is based upon a keyed cryptographic hash function.

Assignees

Inventors

Classifications

  • G06F21/575Primary

    Secure boot · CPC title

  • Assessing vulnerabilities and evaluating computer system security · CPC title

  • Providing cryptographic facilities or services · CPC title

  • involving covert channels, i.e. data leakage between processes (inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755) · CPC title

  • Physics · mapped topic

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What does patent US11429722B2 cover?
An example system with a pre-OS (Operating System) environment, the pre-OS environment includes a private memory that is isolated from a processor of the system. The pre-OS environment also includes an embedded controller (EC) coupled to the private memory, where the EC includes an embedded key. The EC is to execute instructions to generate an encryption key based on the embedded key; generate …
Who is the assignee on this patent?
Hewlett Packard Development Co
What technology area does this patent fall under?
Primary CPC classification G06F21/575. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 30 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).