Data processing device, image reading apparatus, image forming apparatus, and data processing method

Patent metadata

Field	Value
Publication number	US-11429141-B2
Application number	US-202016820728-A
Country	US
Kind code	B2
Filing date	Mar 17, 2020
Priority date	Mar 22, 2019
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A data processing device includes a data processing circuit and a data processing control circuit. The data processing circuit is configured to perform data processing on processing target data by use of an external clock, the processing target data being included in a data signal received from an outside, the external clock being included in the data signal. The data processing control circuit is configured to detect a state of the external clock and control execution of the data processing on the processing target data in accordance with the state of the external clock. The data processing control circuit is configured to operate with a clock having a lower impedance than an impedance of the external clock, and discard the processing target data received during a period in which an abnormality of the external clock is detected, in a case of detecting the abnormality of the external clock.

First claim

The invention claimed is:

1. A data processing device comprising:
a data processing circuit configured to perform data processing on processing target data by use of an external clock, the processing target data being included in a data signal received from an outside, the external clock being included in the data signal;
a data processing control circuit configured to detect a state of the external clock and control execution of the data processing on the processing target data in accordance with the state of the external clock,
the data processing control circuit configured to operate with a clock having a lower impedance than an impedance of the external clock, and discard the processing target data received during a period in which an abnormality of the external clock is detected, in a case of detecting the abnormality of the external clock; and
an internal clock generator including a phase-locked loop (PLL) circuit and configured to generate, from the external clock, an internal clock to be used for operation of the data processing circuit,
wherein the data processing control circuit detects an abnormality of the external clock based on a PLL lock signal output from the PLL circuit,
wherein the data signal is transmitted by a low voltage differential signaling (LVDS) system, and
the data processing device includes an LVDS receiver circuit configured to receive the data signal.

2. The data processing device according to claim 1 ,
wherein the clock having the lower impedance is generated on a circuit board including the data processing control circuit.

3. The data processing device according to claim 2 ,
wherein the data processing control circuit includes a resetting circuit configured to bring the data processing control circuit and the data processing circuit into a reset state when the external clock is abnormal, and
wherein the resetting circuit keeps the data processing control circuit in the reset state for a predetermined period of time or longer.

4. The data processing device according to claim 1 ,
wherein the processing target data includes a synchronization signal for defining a unit of processing.

5. The data processing device according to claim 1 ,
wherein the data processing control circuit includes a resetting circuit configured to bring the data processing control circuit and the data processing circuit into a reset state when the external clock is abnormal.

6. The data processing device according to claim 5 ,
wherein the resetting circuit keeps the data processing control circuit in the reset state for a predetermined period of time or longer.

7. The data processing device according to claim 1 ,
wherein the data processing control circuit detects an abnormality of the external clock when a result of filtering the external clock for a predetermined period of time is abnormal.

8. The data processing device according to claim 1 ,
wherein the data processing control circuit does not detect an abnormality of an external clock for a specific period of time after detecting that the external clock is abnormal.

9. The data processing device according to claim 1 ,
wherein the data processing control circuit operates after completion of an initial setting at a start of operation of the data processing device.

10. The data processing device according to claim 9 ,
wherein the data processing control circuit includes a resetting circuit configured to bring the data processing control circuit and the data processing circuit into a reset state when the external clock is abnormal, and
wherein the resetting circuit keeps the data processing control circuit in the reset state for a predetermined period of time or longer.

11. The data processing device according to claim 1 ,
wherein the processing target data include image data.

12. A data processing method to be performed in a data processing device including a data processing circuit configured to perform data processing on processing target data by use of an external clock, the processing target data being included in a data signal received from an outside, the external clock being included in the data signal, the data processing method comprising:
causing a data processing control circuit to detect a state of the external clock, the data processing control circuit being included in the data processing device and configured to operate with a clock having a lower impedance than an impedance of the external clock;
causing the data processing control circuit to discard the processing target data received during a period in which an abnormality of the external clock is detected, in a case of detecting the abnormality of the external clock;
generating, by an internal clock generator including a phase-locked loop (PLL) circuit, from the external clock, an internal clock to be used for operation of the data processing circuit; and
detecting, by the data processing control circuit, an abnormality of the external clock based on a PLL lock signal output from the PLL circuit,
wherein the data signal is transmitted by a low voltage differential signaling (LVDS) system, and
the data processing device includes an LVDS receiver circuit configured to receive the data signal.

13. An image reading apparatus comprising:
a data acquisition device configured to transmit optically read image data together with a clock signal; and
the data processing device according to claim 1 , configured to receive the image data and the clock signal from the data acquisition device and perform the data processing on the image data by use of the clock signal.

14. An image forming apparatus comprising:
the data processing device according to claim 1 ; and
an image forming device configured to form and output an image on a recording medium by use of data processed by a data processing device configured to perform predetermined data processing on processing target data input from an outside.

15. The data processing device according to claim 1 ,
wherein the data processing control circuit includes a resetting circuit configured to bring the data processing control circuit and the data processing circuit into a reset state when the external clock is abnormal, and
wherein the resetting circuit keeps the data processing control circuit in the reset state for a predetermined period of time or longer.

Assignees

• Sasa Tomohiro
• Tsukahara Hajime
• Ricoh Co Ltd

Inventors

• Sasa Tomohiro
• Tsukahara Hajime

Classifications

• G06F1/14 Primary

  Time supervision arrangements, e.g. real time clock · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/1417

  Boot up procedures · CPC title

• H04N1/00933

  Timing control or synchronising (H04N1/00928, H04N1/00931, H04N1/00954 and H04N1/0096 take precedence) · CPC title

• H04N1/00037

  Detecting, i.e. determining the occurrence of a predetermined state (H04N1/00031 takes precedence) · CPC title