Logic circuitry

Patent metadata

Field	Value
Publication number	US-11427010-B2
Application number	US-201916965231-A
Country	US
Kind code	B2
Filing date	Apr 5, 2019
Priority date	Dec 3, 2018
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A logic circuitry package for a replaceable print apparatus component comprises an interface to communicate with a print apparatus logic circuit, and at least one logic circuit. The logic circuit may be configured to identify, from a command stream received from the print apparatus, parameters including a class parameter, and/or identify, from the command stream, a read request, and output, via the interface, a count value in response to a read request, the count value based on identified received parameters.

First claim

What is claimed is:

1. A logic circuitry package for a replaceable print apparatus component comprising:
an interface to communicate with a print apparatus logic circuit; and
at least one logic circuit, configured to:
identify, from a command stream, a read request;
output, via the interface, a count value (CV) in response to a read request, the count value (CV) based on identified received parameters;
identify, from the command stream received from the print apparatus, parameters including class parameters (CS) and sub-class parameters (SCS);
identify more sub-class parameters (SCS) than class-parameters (CS);
associate at least two classes with at least 40 sub-classes and other classes with not more than one sub-class, wherein communicated sub-classes may the same for different classes; and
output in response to a read request, a count value (CV) based on the last-received class parameter (CS) and sub-class parameter (SCS).

2. The logic circuitry package of claim 1 , wherein the at least one logic circuit is configured to generate, in response to at least one read request:
a first plurality of count values other than the highest or lowest count values in response to receiving a plurality of varying sub-class parameters preceded by the first class parameter, and
a second plurality of count values other than the highest or lowest count values in response to receiving a plurality of varying sub-class parameters preceded by the second class parameter, the second plurality of count values different than the first plurality of count values.

3. The logic circuitry package of claim 1 , wherein the logic circuit is configured to output a series of different count values in response to receiving a corresponding series of different sub-class parameters, following receiving a class parameter and certain operational calibration parameters for that class.

4. The logic circuitry package of claim 1 , wherein the logic circuit is configured to:
identify a first or second class parameter associated with a first or second class;
upon identifying the first or second class parameter, select a respective first or second class;
identify a series of sub-class parameters and read requests while the respective first or second class is selected, and, in response to each read request, output a count value for each corresponding selected subclass;
identify a third or fourth class parameter associated with a third or fourth class; and
upon identifying the third or fourth class parameter and a subsequent read request, output a respective count value, wherein any sub-class parameter received between receiving the third or fourth class parameter and read request does not affect the output count value.

5. The logic circuitry package of claim 1 , wherein each parameter is defined by a function and a value wherein the parameter function is encoded in one data frame of a command and the parameter value is encoded in another data frame of the command,
wherein the logic circuit includes a plurality of logic functions to apply input parameters, and the logic circuit is configured to select a logic function based on the identified parameter function and assign the identified parameter value to the selected logic function.

6. The logic circuitry package of claim 5 , wherein the logic circuit includes decoding logic to identify parameters, the decoding logic including different memory fields having different addresses to store parameter values, which addresses are addressed by respective parameter functions, wherein each memory field address is associated with at least one corresponding logic function.

7. The logic circuitry package of claim 5 , wherein the logic circuit is configured to identify a sub-class parameter value based on not more than the least significant and six following bits (6:0) in an eight bit data frame so that seven bits including the least significant bit affect the output count value, while the most significant bit in the data frame does not affect the output count value.

8. The logic circuitry package of claim 1 , wherein the logic circuit is configured to generate the count value using received parameters and based on at least one, or a combination, of
a look-up table (LUT),
an algorithm, and
a physical sensor cell.

9. The logic circuitry package of claim 8 , wherein the logic circuit is configured to relate received parameters (CS, SCS) to an output count value (CV) using said at least one or combination of LUT, algorithm and physical sensor cell.

10. The logic circuitry package of claim 9 , wherein the logic circuit is configured to consult at least one sensor cell to:
detect a pneumatic stimulus upon identifying the first class parameter, and to relate the sensor signal as well as the other received parameters to an output count value to generate the related output count value (CV), and/or
relate the sensor signal as well as the other received parameters to an output count value to generate the related output count value (CV), upon identifying the second class parameter.

11. The logic circuitry package of claim 10 , wherein the logic circuit is configured to consult the same sensor cell based on different sub-class parameters.

12. The logic circuitry package of claim 1 , configured to:
receive a command specifying a time parameter, the command directed to a first, default I2C communications address of the package which is to distinguish the component from other components installed in the same print apparatus in communications over a serial bus; and
in response to the command, enable the processing of a command stream directed to a second default and/or new I2C communications address for a duration based on the time parameter.

13. The logic circuitry package of claim 12 , wherein the logic circuit is configured to, in response to the command stream to the second address, for different parameters associated with different functions, apply the last received parameter for conditioning the output until it receives a new respective parameter, at least for the duration.

14. The logic circuitry package of claim 12 , wherein said command stream is directed to the second and/or new I2C communications address, and the logic circuitry package configured to, after the duration, again, process commands directed to the first I2C communications address.

15. The logic circuitry package of claim 12 , further including a timer and/or delay circuit, to determine the duration.

16. The logic circuitry package of claim 12 , wherein the logic circuit is configured to transmit, outside of said duration and in response to communications sent to the first address, communications that are authenticated using a base key, and, during said duration and in response to communications sent to the second or new address, communications which are not authenticated using that base key.

17. The logic circuitry package of claim 1 , wherein the logic circuit is configured to output said different count values in a range defined by a lowest and highest count values and a plurality of count values in between, wherein the lowest output count value of the range is a binary representation of 0 and the highest output count value is a binary representation of 255.

18. The logic circuitry package of claim 1 , further including a sensor to detect an effect of a pneumatic stimulus, the logic circuit configured to consult the sensor in response to identifying a class parameter associated with a first class.

19. The logic circuitry package of claim 18 , wherein the logic cir

Assignees

• Hewlett Packard Development Co

Inventors

• Gardner James Michael
• Linn Scott A
• Panshin Stephen D
• Ward Jefferson P
• Roethig David Owen
• Olsen David N
• Studer Anthony D
• Cumbie Michael W
• Lu Sirena Chi

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• H04L9/0819

  Key transport or distribution, i.e. key establishment techniques where one party creates or otherwise obtains a secret value, and securely transfers it to the other(s) (network architectures or network communication protocols for key distribution in a packet data network H04L63/062) · CPC title

• B41J2202/20

  Modules · CPC title

• G06F9/30105

  Register structure · CPC title

• G06F21/62

  Protecting access to data via a platform, e.g. using keys or access control rules · CPC title