Systems and methods for all-digital phase locked loop

Patent metadata

Field	Value
Publication number	US-11424747-B2
Application number	US-202117159124-A
Country	US
Kind code	B2
Filing date	Jan 26, 2021
Priority date	Jan 27, 2020
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

An all-digital phase locked loop (ADPLL) is provided. The ADPLL comprises a pattern generator adapted to generate a frequency control word (FCW) based on a predefined setting and a system clock. In addition, the ADPLL comprises a phase accumulator adapted to translate the FCW into a phase trajectory. The ADPLL further comprises a phase comparator adapted to generate a phase error signal representing a difference between the phase trajectory and the phase of an output oscillation frequency. Moreover, the ADPLL comprises a controller adapted to control a phase of the output oscillation frequency with respect to the phase trajectory.

First claim

What is claimed is:

1. An all-digital phase locked loop comprising:
a pattern generator configured to generate a frequency control word based on a predefined setting and a system clock;
a phase accumulator configured to translate the frequency control word into a phase trajectory;
a phase comparator configured to generate a phase error signal representing a difference between the phase trajectory and a phase of an output oscillation frequency;
a controller configured to control the phase of the output oscillation frequency with respect to the phase trajectory; and
a loop filter adapted to generate control signals towards the controller based on the phase error signal and a modulating signal calculated from the phase trajectory.

2. The all-digital phase locked loop according to claim 1 , further comprising:
a differentiator adapted to calculate the modulating signal from the phase trajectory.

3. The all-digital phase locked loop according to claim 1 , wherein the controller comprises a Process-Voltage-Temperature capacitor bank, an Acquisition capacitor bank, and a Tracking capacitor bank, and wherein the controller is further adapted to exchange capacitance between the Process-Voltage-Temperature capacitor bank and the Acquisition capacitor bank, and between the Acquisition capacitor bank and the Tracking capacitor bank in order to increase their effective range.

4. The all-digital phase locked loop according to claim 1 , wherein the phase trajectory translated from the frequency control word is predictable in both timing and amplitude over a number of channels to be measured.

5. The all-digital phase locked loop according to claim 4 , wherein the phase accumulator is further adapted to receive a relock command in order to relock the all-digital phase locked loop to the phase trajectory when switching over the number of channels to be measured.

6. The all-digital phase locked loop according to claim 4 , wherein the controller comprises a modulation bank respecting a frequency span of the number of channels to be measured.

7. The all-digital phase locked loop according to claim 1 , wherein the phase accumulator further comprises a first phase accumulator and a second phase accumulator respectively operable on a transmit mode and a receive mode or vice versa.

8. The all-digital phase locked loop according to claim 1 , wherein the phase accumulator further comprises a compensation unit adapted to calculate a respective phase trajectory for a transmit mode or a receive mode.

9. A wireless communication system comprising a first radio node and a second radio node, each comprising the all-digital phase locked loop of claim 1 , wherein the first radio node is operable on a transmit mode and the second radio node is operable on a receive mode or vice versa.

10. The wireless communication system according to claim 9 , wherein the first radio node and the second radio node are adapted to switch between the transmit mode and the receive mode through a number of channels to be measured in order to measure a phase at each channel.

11. A method for maintaining phase lock of an all-digital phase locked loop along a predictable phase trajectory, the method comprising:
generating a frequency control word by a pattern generator based on a predefined setting and a system clock;
translating the frequency control word into a phase trajectory by a phase accumulator;
generating a phase error signal by a phase comparator representing a difference between the phase trajectory and a phase of an output oscillation frequency; and
controlling the phase of the output oscillation frequency by a controller with respect to the phase trajectory, and
generating, by a loop filter, control signals towards the controller based on the phase error signal and a modulating signal calculated from the phase trajectory.

12. The method according to claim 11 , wherein the method further comprises:
calculating, by a differentiator, the modulating signal from the phase trajectory.

13. The method according to claim 11 ,
wherein the controller comprises a Process-Voltage-Temperature capacitor bank, an Acquisition capacitor bank, and a Tracking capacitor bank, and
wherein the method further comprises a step of exchanging capacitance between the Process-Voltage-Temperature capacitor bank and the Acquisition capacitor bank, and between the Acquisition capacitor bank and the Tracking capacitor bank by the controller, thereby increasing their effective range.

14. The method according to claim 13 , wherein the method further comprises:
setting an output of the phase comparator to zero in order to maintain a phase lock while exchanging capacitance.

15. The method according to any of claim 11 , wherein the method further comprises:
translating the phase trajectory from the frequency control word in a predictable manner in both timing and amplitude over a number of channels to be measured.

16. The method according to claim 12 , wherein:
the differentiator is coupled to an output path of the phase accumulator,
the method further comprises:
receiving the predefined setting at the differentiator,
performing, at the differentiator, a reverse operation of the phase accumulator to reconstruct the frequency control word from the phase trajectory, and

the differentiator calculates the modulating signal by subtracting the predefined setting from the reconstructed frequency control word.

17. The method according to claim 12 , further comprising:
receiving, at the differentiator, a modulation index and a receive-mode/transmit-mode control signal,
wherein calculating the modulating signal is based on the modulation index and the receive-mode/transmit-mode control signal.

18. The all-digital phase locked loop according to claim 2 , wherein:
the differentiator is coupled to an output path of the phase accumulator,
the differentiator is adapted to receive the predefined setting and to perform a reverse operation of the phase accumulator to reconstruct the frequency control word from the phase trajectory, and
the differentiator calculates the modulating signal by subtracting the predefined setting from the reconstructed frequency control word.

19. The all-digital phase locked loop according to claim 2 , wherein:
the differentiator is adapted to receive a modulation index and a receive-mode/transmit-mode control signal, and
calculating the modulating signal is based on the modulation index and the receive-mode/transmit-mode control signal.

Assignees

• Stichting Imec Nederland

Inventors

• Van Den Heuvel Johan
• Bechthum Elbert

Classifications

• H03L7/16

  Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop · CPC title

• H03C3/095

  applying frequency modulation to the loop in front of the voltage controlled oscillator · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title