Multi-spacers for quantum dot device gates

Patent metadata

Field	Value
Publication number	US-11424324-B2
Application number	US-201816144148-A
Country	US
Kind code	B2
Filing date	Sep 27, 2018
Priority date	Sep 27, 2018
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a multi-spacer between the first gate and the second gate, wherein the multi-spacer includes a first spacer and a second spacer different from the first spacer, and the first spacer is at least partially between the quantum well stack and the second spacer.

First claim

The invention claimed is:

1. A quantum dot device, comprising:
a quantum well stack;
a first gate and an adjacent second gate above the quantum well stack; and
a multi-spacer between the first gate and the second gate, wherein the multi-spacer includes a first spacer and a second spacer different from the first spacer, the first spacer is at least partially between the quantum well stack and the second spacer, a portion of the second spacer has a thickness above the first spacer, and the thickness is between 5 nanometers and 20 nanometers.

2. The quantum dot device of claim 1 , wherein the first spacer includes carbon, nitrogen, silicon, or oxygen.

3. The quantum dot device of claim 1 , wherein the second spacer has a same material composition as the first spacer.

4. The quantum dot device of claim 1 , wherein the second spacer has a different material composition than the first spacer.

5. The quantum dot device of claim 1 , wherein a bottom surface of the first spacer is coplanar with a bottom surface of the second spacer.

6. The quantum dot device of claim 1 , wherein a bottom surface of the first spacer is non-coplanar with a bottom surface of the second spacer.

7. The quantum dot device of claim 1 , wherein a bottom surface of the second spacer provides a shoulder extending away from a side surface of the first spacer.

8. The quantum dot device of claim 1 , wherein the first gate includes a first gate metal and a first gate dielectric, and the first gate dielectric is at least partially between the first gate metal and the first spacer.

9. The quantum dot device of claim 8 , wherein the first gate dielectric is at least partially between the first gate metal and the second spacer.

10. The quantum dot device of claim 8 , wherein the first gate dielectric has a U-shaped cross-section.

11. The quantum dot device of claim 8 , wherein the second gate includes a second gate metal and a second gate dielectric, and the second gate dielectric is at least partially between the second gate metal and the first spacer.

12. The quantum dot device of claim 11 , wherein the second gate dielectric is at least partially between the second gate metal and the second spacer.

13. The quantum dot device of claim 1 , wherein at least a portion of the second spacer is conformal on a surface of the first spacer.

14. The quantum dot device of claim 1 , wherein a portion of the first spacer is between a portion of the second spacer and the first gate.

15. The quantum dot device of claim 14 , wherein the portion of the second spacer is between the portion of the first spacer and the second gate.

16. The quantum dot device of claim 1 , wherein the quantum well stack is at least partially included in a fin, or the first gate and the second gate are at least partially disposed in a trench in an insulating material above the quantum well stack.

17. The quantum dot device of claim 1 , wherein:
the quantum dot device is a quantum computing device,
the quantum computing device includes a quantum processing device and a non-quantum processing device,
the quantum processing device includes the quantum well stack, the first gate, the second gate, and the multi-spacer, and
the non-quantum processing device is coupled to the quantum processing device and is to control voltages applied to the first gate and the second gate.

18. The quantum computing device of claim 17 , further comprising:
a memory device to store data generated by quantum dots formed in the quantum well stack during operation of the quantum processing device.

19. The quantum computing device of claim 18 , wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

20. The quantum computing device of claim 17 , further comprising:
a cooling apparatus to maintain a temperature of the quantum processing device below 5 Kelvin.

21. A method of manufacturing a quantum dot device, comprising:
forming a quantum well stack;
providing a first gate and an adjacent second gate above the quantum well stack; and
providing a multi-spacer between the first gate and the second gate, wherein the multi-spacer includes a first spacer and a second spacer different from the first spacer, the first spacer is at least partially between the quantum well stack and the second spacer, a portion of the second spacer has a thickness above the first spacer, and the thickness is between 5 nanometers and 20 nanometers.

22. A quantum dot device, comprising:
a quantum well stack;
a first gate and an adjacent second gate above the quantum well stack; and
a multi-spacer between the first gate and the second gate, wherein the multi-spacer includes a first spacer and a second spacer different from the first spacer, the first spacer is at least partially between the quantum well stack and the second spacer, and a bottom surface of the second spacer provides a shoulder extending away from a side surface of the first spacer.

23. The quantum dot device of claim 22 , wherein a bottom surface of the first spacer is non-coplanar with a bottom surface of the second spacer.

24. A quantum dot device, comprising:
a quantum well stack;
a first gate and an adjacent second gate above the quantum well stack;
a first spacer; and
a second spacer, different from the first spacer, wherein:
the first spacer is at least partially between the first gate and the second spacer,
the second spacer is at least partially between the first spacer and the second gate,
the first spacer is at least partially between the quantum well stack and the second spacer,
a portion of the second spacer has a thickness above the first spacer, and
the thickness is between 5 nanometers and 20 nanometers.

25. The quantum dot device of claim 24 , wherein the first gate includes a first gate metal and a first gate dielectric, and the first gate dielectric is at least partially between the first gate metal and the first spacer.

Assignees

• Intel Corp

Inventors

• George Hubert C
• Pillarisetty Ravi
• Lampert Lester
• Clarke James S
• Thomas Nicole K
• Caudillo Roman
• Michalak David J
• Roberts Jeanette M

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10D48/3835

  Semiconductor qubit devices comprising a plurality of quantum mechanically interacting semiconductor quantum dots, e.g. Loss-DiVincenzo spin qubits · CPC title