Capacitor devices and fabrication methods thereof

US11424318B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11424318-B2
Application numberUS-201916538100-A
CountryUS
Kind codeB2
Filing dateAug 12, 2019
Priority dateSep 28, 2018
Publication dateAug 23, 2022
Grant dateAug 23, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for fabricating a capacitor device includes providing a substrate; forming a first-layer electrode on the substrate; and forming a conductive layer on the first-layer electrode. The roughness of the first-layer electrode is a first roughness, the roughness of the conductive layer is a second roughness, and the second roughness is smaller than the first roughness. The method further includes forming a dielectric layer on the conductive layer; and forming a second-layer electrode on the dielectric layer. According to the disclosed method and capacitor device, by forming the conductive layer on the first-layer electrode, the roughness of the bottom electrode of the capacitor device is reduced, which effectively reduces the presence of protrusions on the surface of the bottom electrode. Therefore, the breakdown electric voltage of the capacitor device may be improved, and leakage current may be avoided. As such, the reliability of the capacitor device may be improved.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for fabricating a capacitor device, comprising: providing a substrate; forming a first-layer electrode on the substrate, wherein a roughness of the first-layer electrode is a first roughness; after forming the first-layer electrode, performing a first surface treatment process on a surface of the first-layer electrode, wherein the first surface treatment process includes a wet cleaning process and a dry cleaning process, and an inert-gas treatment process after the wet cleaning process and the dry cleaning process; after performing the first surface treatment process on a surface of the first-layer electrode, forming a conductive layer directly on the first-layer electrode, wherein the first-layer electrode is directly sandwiched by the substrate and the conductive layer, the conductive layer is capable of self-planarization to fill into gaps between protrusions of the first-layer electrode, a roughness of the conductive layer is a second roughness, and the second roughness is smaller than the first roughness; after forming the conductive layer performing a second surface treatment process on a surface of the conductive layer; forming a dielectric layer on the conductive layer, wherein the second surface treatment process is performed before forming the dielectric layer and performing the second surface treatment process includes performing a reducing-gas treatment process, wherein a reducing gas used in the reducing-gas treatment process includes one or a combination of hydrogen, carbon monoxide, hydrogen sulfide, methane, and sulfur monoxide; performing a third surface treatment process on a surface of the dielectric layer, wherein performing the third surface treatment process includes: performing a cleaning process including a combination of a wet cleaning process and a dry cleaning process; and forming a second-layer electrode on the dielectric layer. 2. The method according to claim 1 , wherein: the first-layer electrode is made of a first metal nitride; the second-layer electrode is made of a second metal nitride; a thickness of the first-layer electrode is in a range of approximately 100 Å to 1000 Å; and a thickness of the second-layer electrode is in a range of approximately 100 Å to 1000 Å. 3. The method according to claim 2 , wherein: the first metal nitride includes one or more of titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, and cobalt nitride, and the second metal nitride includes one or more of titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, and cobalt nitride. 4. The method according to claim 1 , wherein: a process of forming the first-layer electrode includes an atomic layer deposition (ALD) process, a plasma chemical vapor deposition (PCVD) process, a low-pressure chemical vapor deposition (LPCVD) process, a sputtering deposition process, an ion beam deposition process, or an ion-beam assisted deposition process; and a process of forming the second-layer electrode includes an ALD process, a PCVD process, a LPCVD process, a sputtering deposition process, an ion beam deposition process, or an ion-beam assisted deposition process. 5. The method according to claim 1 , wherein: a thickness of the conductive layer is in a range of approximately 10 Å to 1000 Å. 6. The method according to claim 1 , wherein: the conductive layer is made of a metal. 7. The method according to claim 6 , wherein: the metal includes one or more of copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, and platinum. 8. The method according to claim 1 , wherein: a process of forming the conductive layer includes a sputtering deposition process, an ion beam deposition process, or an ion-beam assisted deposition process. 9. The method according to claim 1 , wherein: the dielectric layer is made of a high-k dielectric material; and a thickness of the dielectric layer is in a range of approximately 10 Å to 200 Å. 10. The method according to claim 1 , wherein: a plurality of semiconductor devices is formed in the substrate. 11. The method according to claim 1 , wherein: the second surface treatment process is performed on the surface of the conductive layer to prevent the conductive layer from being oxidized and prevent the capacitor device from degrading to a low capacitance density.

Assignees

Inventors

Classifications

  • using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title

  • Physical vapour deposition [PVD] · CPC title

  • Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

  • H10D1/696Primary

    comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

  • H10D1/712Primary

    being rough surfaces, e.g. using hemispherical grains · CPC title

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What does patent US11424318B2 cover?
A method for fabricating a capacitor device includes providing a substrate; forming a first-layer electrode on the substrate; and forming a conductive layer on the first-layer electrode. The roughness of the first-layer electrode is a first roughness, the roughness of the conductive layer is a second roughness, and the second roughness is smaller than the first roughness. The method further inc…
Who is the assignee on this patent?
Semiconductor Mfg Int Shanghai Corp, Semiconductor Mfg Int Beijing Corp
What technology area does this patent fall under?
Primary CPC classification H10D1/696. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 23 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).