Flexible display panel having mask-etching metal connection line in display and non-display areas and fabricating method thereof

Patent metadata

Field	Value
Publication number	US-11424311-B2
Application number	US-202016769701-A
Country	US
Kind code	B2
Filing date	Feb 19, 2020
Priority date	Dec 12, 2019
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

A flexible display panel and a fabricating method thereof are provided. The fabricating method has: disposing an active layer and a gate of a switching tube of the flexible display panel sequentially on a substrate, wherein the switching tube is in the display area; disposing a source and a drain on the gate, wherein a signal connection line at same layer as the source and the drain is disposed in the non-display area; disposing a first insulating layer and a metal connection line sequentially on the source and the drain, wherein the first insulating layer and/or the metal connection line further extends into the non-display area and covers the signal connection line. This application increases thickness of film layers on the signal connection line, and also avoids phenomenon that the signal connection line is etched away due to over-etching upon etching the metal connection line, thereby causing disconnection phenomenon.

First claim

What is claimed is:

1. A fabricating method of a flexible display panel, the flexible display panel comprising a display area and a non-display area including an IC area and a test binding area, the fabricating method comprising steps of:
providing a substrate;
disposing an active layer and a gate of a switching tube of the flexible display panel sequentially on the substrate, wherein the switching tube is in the display area;
disposing a source and a drain of the switching tube on the gate, wherein a signal connection line at a same layer as the source and the drain is disposed in the non-display area, and the signal connection line electrically connects the source or the drain to an external test circuit; and
disposing a first insulating layer and a metal connection line sequentially on the source and the drain, wherein a pixel electrode layer is disposed on the metal connection line, and the metal connection line is electrically connected to the source or the drain to transmit a signal of the source or the drain to the pixel electrode layer, wherein the first insulating layer and/or the metal connection line further extends from the IC area into the test binding area and the metal connection line in the test binding area directly covers the signal connection line.

2. The fabricating method according to claim 1 , wherein the step of disposing the first insulating layer and/or the metal connection line further extending from the IC area into the test binding area and the metal connection line in the test binding area directly covering the signal connection line comprises:
disposing the first insulating layer and the metal connection line sequentially on the source and the drain by mask etching, respectively, so that the first insulating layer and/or the metal connection line on the signal connection line located in the non-display area remain after the mask etching.

3. The fabricating method according to claim 1 , wherein before the step of disposing the source and the drain of the switching tube on the gate, the fabricating method comprises:
disposing a storage electrode on the gate, and the storage electrode and the gate form a storage capacitor.

4. The fabricating method according to claim 3 , wherein before the step of disposing the storage capacitor on the gate, the fabricating method comprises:
disposing a second insulating layer on the gate;
wherein the step of disposing the storage electrode on the gate comprises:
disposing the storage electrode on the second insulating layer;
wherein before the step of disposing the source and the drain of the switching tube on the gate, the method comprises:
disposing a third insulating layer on the storage electrode;
wherein the fabricating method further includes:
disposing a fourth insulating layer on the active layer;
wherein the step of disposing the source and the drain of the switching tube on the gate comprises:
disposing two via holes on the second insulating layer, the third insulating layer, and the fourth insulating layer, and the two via holes respectively expose two ends of the active layer, wherein the source and the drain are disposed on the third insulating layer, and the source and the drain are electrically connected to the active layer through the two via holes, respectively.

5. The fabricating method according to claim 4 , further comprising:
disposing a first filling hole in the substrate, and disposing a second filling hole in the second insulating layer, the third insulating layer, and the fourth insulating layer, wherein the first filling hole and the second filling hole are connected to each other; and
disposing flexible material to fill in the first filling hole and the second filling hole.

6. A flexible display panel, comprising a display area and a non-display area including an IC area and a test binding area, the flexible display panel further comprising:
a substrate;
an active layer and a gate of a switching tube disposed sequentially on the substrate, wherein the switching tube is in the display area;
a source and a drain of the switching tube disposed on the gate;
a signal connection line disposed in the non-display area and at a same layer as the source and the drain, wherein the signal connection line electrically connects the source or the drain to an external test circuit; and
a first insulating layer and a metal connection line disposed sequentially on the source and the drain, wherein a pixel electrode layer is disposed on the metal connection line, and the metal connection line is electrically connected to the source or the drain to transmit a signal of the source or the drain to the pixel electrode layer, wherein the first insulating layer and/or the metal connection line further extends from the IC area into the test binding area and the metal connection line in the test binding area directly covers the signal connection line.

7. The flexible display panel according to claim 6 , wherein the flexible display panel further comprises:
a storage electrode disposed on the gate, and the storage electrode and the gate form a storage capacitor.

8. The flexible display panel according to claim 7 , wherein the flexible display panel further comprises:
a second insulating layer disposed on the gate, wherein the storage electrode is disposed on the second insulating layer;
a third insulating layer is disposed on the storage capacitor; and
a fourth insulating layer is disposed on the active layer.

9. The flexible display panel according to claim 8 , wherein the flexible display panel further comprises:
two via holes disposed on the second insulating layer, the third insulating layer, and the fourth insulating layer, wherein the two via holes respectively expose two ends of the active layer, wherein the source and the drain are disposed on the third insulating layer, and the source and the drain are electrically connected to the active layer through the two via holes, respectively.

10. The flexible display panel according to claim 9 , wherein the flexible display panel further comprises:
a first filling hole disposed in the substrate, and a second filling hole disposed in the second insulating layer, the third insulating layer, and the fourth insulating layer, wherein the first filling hole and the second filling hole are connected to each other, and flexible material is disposed to fill in the first filling hole and the second filling hole.

Assignees

• Wuhan China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Ming Xing

Classifications

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/124 Primary

  Insulating layers formed between TFT elements and OLED elements · CPC title

• G09F9/301

  flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED · CPC title

• H01L2227/323

  Electricity · mapped topic

• H01L51/52

  Electricity · mapped topic