Device including a floating gate electrode and a layer of ferroelectric material and method for the formation thereof

Patent metadata

Field	Value
Publication number	US-11424253-B2
Application number	US-201815864581-A
Country	US
Kind code	B2
Filing date	Jan 8, 2018
Priority date	Aug 26, 2014
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

An illustrative device disclosed herein includes a semiconductor substrate. The substrate includes a source region, a drain region and a channel region. The channel region is arranged between the source region and the drain region. A gate insulation layer is provided over the channel region. A floating gate electrode is provided over the gate insulation layer. A layer of a ferroelectric material is provided over the floating gate electrode. A top electrode is provided over the layer of ferroelectric material. A projected area of the top electrode onto a plane that is perpendicular to a thickness direction of the semiconductor substrate is smaller than a projected area of the floating gate electrode onto the plane.

First claim

The invention claimed is:

1. A device comprising:
a semiconductor substrate comprising a source region, a drain region, and a channel regions, the channel region being arranged between the source region and the drain region;
a gate insulation layer provided over the channel region;
a floating gate electrode provided over the gate insulation layer;
an oxide layer provided over the floating gate electrode, the oxide layer comprising a ferroelectric material including as main components, oxygen and any of the group consisting of Hf, Zr and (Hf,Zr);
a top electrode provided over the oxide layer, wherein a projected area of the top electrode onto a plane that is perpendicular to a thickness direction of the semiconductor substrate is smaller than a projected area of the floating gate electrode onto said plane; and
a dielectric liner layer disposed over the top electrode and having portions extending perpendicularly to the channel direction to enclose sides of the top electrode and the oxide layer perpendicular to the thickness direction of the semiconductor substrate, wherein the dielectric liner layer encloses a first portion of a perimeter side of a single layer of a same material of the floating gate electrode and a remaining portion of the perimeter side of the single layer of the floating gate electrode is exposed from the dielectric liner layer, wherein the floating gate electrode includes a first metal layer having perimeter sides exposed from the dielectric liner layer, and a second metal layer disposed above the first metal layer and having perimeter sides enclosed by the dielectric liner layer, the single layer is disposed between the first and second metal layers.

2. The device according to claim 1 , wherein the floating gate electrode comprises at least one of tantalum nitride, titanium nitride and polysilicon.

3. The device according to claim 1 , wherein the gate insulation layer includes a material having a greater dielectric constant than silicon dioxide.

4. The device according to claim 1 , wherein each of the floating gate electrode and the top electrode comprises a titanium nitride layer and a polysilicon layer, the polysilicon layer being arranged above the titanium nitride layer.

5. The device according to claim 1 , further comprising a second liner layer, the second liner layer being provided over the source and drain regions and adjacent the floating gate electrode.

6. The device of claim 1 , wherein the single layer of the floating gate electrode having the first portion of the perimeter side enclosed by the dielectric liner layer and the remaining portion of the perimeter side exposed from the dielectric liner layer is a polysilicon layer.

7. The device of claim 1 , the oxide layer comprising a ferroelectric material including one of hafnium dioxide and zirconium dioxide doped with one of any of the group consisting of Si, Al, Sr, Yt, and Gd.

8. The device of claim 1 , the ferroelectric dielectric layer having a polarization representative of a bit store value.

9. The device of claim 1 , the ferroelectric dielectric layer having an amorphous to crystalline ferroelectric transition temperature at which the ferroelectric properties are attained in a range from 300° C. to 800° C.

Assignees

• Fraunhofer Ges Forschung
• Namlab Ggmbh

Inventors

• Mueller Johannes
• Mueller Stefan
• Flachowsky Stefan

Classifications

• H10D30/68

  Floating-gate IGFETs · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D30/0415

  of FETs having ferroelectric gate insulators · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title