Memory system and management method of characteristic information of semiconductor device

Patent metadata

Field	Value
Publication number	US-11424004-B2
Application number	US-202117190906-A
Country	US
Kind code	B2
Filing date	Mar 3, 2021
Priority date	Jul 2, 2020
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

A memory system includes a non-volatile memory and a memory controller that controls the non-volatile memory. The memory controller includes a monitor circuit to generate a monitor signal indicating at least one characteristic that varies based on a variation in a manufacturing process condition under which the memory controller was manufactured; a digitization circuit to digitize the monitor signal at a plurality of timings to generate a plurality of digitized monitor signals, each of the plurality of digitized monitor signals having a first size; and a compression circuit to compress the plurality of digitized monitor signals data into first data having the first size.

First claim

What is claimed is:

1. A memory system comprising:
a non-volatile memory; and
a memory controller configured to control the non-volatile memory, the memory controller including:
at least one monitor circuit configured to generate a monitor signal indicating at least one characteristic that varies based on a variation in a manufacturing process condition under which the memory controller was manufactured;
a digitization circuit configured to digitize the monitor signal at a plurality of timings to generate a plurality of digitized monitor signals, each of the plurality of digitized monitor signals having a first size; and
a compression circuit configured to compress the plurality of digitized monitor signals into first data having the first size.

2. The memory system according to claim 1 , wherein
the memory controller has a test mode for testing an operation of an internal circuit, and
the plurality of digitized monitor signals are generated during a first period during which the memory controller is operating in the test mode.

3. The memory system according to claim 1 , wherein
the monitor circuit is further configured to:
output the monitor signal with a first characteristic in a case where the memory controller was manufactured under a first manufacturing process condition and the memory controller operates at a first operating voltage at a first temperature, and
output the monitor signal with a second characteristic different from the first characteristic in a case where the memory controller was manufactured under a second manufacturing process condition different from the first manufacturing process condition and the memory controller operates at the first operating voltage at the first temperature.

4. The memory system according to claim 1 , wherein
the at least one monitor circuit includes a plurality of monitor circuits, and
the digitization circuit is configured to digitize the monitor signal of each of the plurality of monitor circuits.

5. The memory system according to claim 1 , wherein
the monitor circuit is configured to adjust a frequency of output of the generated monitor signal.

6. The memory system according to claim 1 , wherein
the compression circuit is configured to compress the plurality of digitized monitor signals in a time domain.

7. The memory system according to claim 1 , wherein
the compression circuit is configured to signature-compress the plurality of digitized monitor signals in a time domain.

8. The memory system according to claim 1 , wherein
the compression circuit is configured to compress the plurality of digitized monitor signals into the first data having the first size regardless of the number of the plurality of digitized monitor signals.

9. The memory system according to claim 1 , wherein
the monitor circuit includes at least one of a ring oscillator, a delay circuit, or a voltage dividing circuit configured for digitizing an internal voltage value.

10. A management method of characteristic information of a semiconductor device, the semiconductor device including at least one monitor circuit, a digitization circuit, and a compression circuit, the method comprising:
executing a first test at a first operating voltage and a first operating temperature on a plurality of semiconductor devices;
instructing the at least one monitor circuit to generate, during the first test, a monitor signal indicating at least one characteristic that varies based on a variation in a manufacturing process condition under which the semiconductor device was manufactured;
instructing the digitization circuit to digitize, during the first test, the monitor signal at a plurality of timings to generate a plurality of digitized monitor signals, each of the plurality of digitized monitor signals having a first size;
instructing the compression circuit to compress, during the first test, the plurality of digitized monitor signals into characteristic information having the first size;
obtaining the characteristic information from each of the plurality of semiconductor devices; and
associating, in a storage device, identification information of each of the plurality of semiconductor devices and the characteristic information of each of the plurality of semiconductor devices with each other.

11. The management method according to claim 10 , further comprising:
storing, in the storage device, the characteristic information obtained from each of a plurality of first semiconductor devices determined to be non-defective among the plurality of semiconductor devices; and
executing a second test on a second semiconductor device different from the plurality of first semiconductor devices, when the characteristic information obtained from the second semiconductor device is different from any of the characteristic information obtained from each of the plurality of first semiconductor devices stored in the storage device.

12. The management method according to claim 10 , further comprising:
storing, in the storage device, the characteristic information obtained from each of the plurality of first semiconductor devices determined to be non-defective among the plurality of semiconductor devices; and
determining that a second semiconductor device as a defective product, the second semiconductor device being different from the plurality of first semiconductor devices, when the characteristic information obtained from the second semiconductor device is different from any of the characteristic information obtained from each of the plurality of first semiconductor devices stored in the storage device.

13. A memory controller comprising:
at least one monitor circuit configured to generate a monitor signal indicating at least one characteristic that varies based on a variation in a manufacturing process condition under which the memory controller was manufactured;
a digitization circuit configured to digitize the monitor signal at a plurality of timings to generate a plurality of digitized monitor signals, each of the plurality of digitized monitor signals having a first size; and
a compression circuit configured to compress the plurality of digitized monitor signals into first data having the first size.

14. The memory controller according to claim 13 , wherein
the memory controller has a test mode for testing an operation of an internal circuit, and
the plurality of digitized monitor signals are generated during a first period during which the memory controller is operating in the test mode.

15. The memory controller according to claim 13 , wherein
the monitor circuit is further configured to:
output the monitor signal with a first characteristic in a case where the memory controller was manufactured under a first manufacturing process condition and the memory controller operates at a first operating voltage at a first temperature, and
output the monitor signal with a second characteristic different from the first characteristic in a case where the memory controller was manufactured under a second manufacturing process condition different from the first manufacturing process condition and the memory controller operates at the first operating voltage at the first temperature.

16. The memory controller according to claim 13 , wherein
the monitor circuit is configured to adjust a frequency of output of the generated monitor signal.

17. The memory controller according to claim 13 , wherein
the compression circuit is configured to compress the plurality of digitized monitor signals in a time domain.

18. The mem

Assignees

• Kioxia Corp

Inventors

• Mori Junji

Classifications

• G11C29/70

  Masking faults in memories by using spares or by reconfiguring · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/50012 Primary

  of timing · CPC title