Processing-in-memory devices for element-wise multiplication

Patent metadata

Field	Value
Publication number	US-11423959-B2
Application number	US-202117319660-A
Country	US
Kind code	B2
Filing date	May 13, 2021
Priority date	Jan 11, 2021
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

A processing-in-memory (PIM) device includes a multiplier circuit, a memory circuit, and an address pipeline circuit. The multiplier circuit is configured to perform an element-wise multiplication (EWM) calculation of first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the multiplier circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.

First claim

What is claimed is:

1. A processing-in-memory (PIM) device comprising:
a multiplier circuit configured to perform an element-wise multiplication (EWM) calculation of first input data and second input data to generate result data;
a memory circuit configured to output the first input data and the second input data to the multiplier circuit in response to a read control signal and configured to store the result data in response to a write control signal; and
an address pipeline circuit configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored and configured to receive the write control signal to output the target address signal to the memory circuit.

2. The PIM device of claim 1 , further comprising a command/address decoder configured to generate control signals and the address signal in response to an EWM command.

3. The PIM device of claim 2 , wherein:
the read control signal, an arithmetic control signal, and the write control signal are included in the control signals; and
the command/address decoder is configured to sequentially output the read control signal, the arithmetic control signal, and the write control signal.

4. The PIM device of claim 3 , wherein the command/address decoder is configured to:
transmit both the read control signal and the write control signal to each of the memory circuit and the address pipeline circuit; and
transmit the arithmetic control signal to the multiplier circuit.

5. The PIM device of claim 4 , wherein the command/address decoder is configured to transmit all of the read control signal, the write control signal, and the address signal to each of the memory circuit and the address pipeline circuit.

6. The PIM device of claim 2 ,
wherein the command/address decoder includes a mode register set having a first predetermined value used for a memory access operation and a second predetermined value used for the EWM calculation; and
wherein the second predetermined value of the mode register set is activated when the EWM calculation is requested.

7. The PIM device of claim 1 , wherein the multiplier circuit is configured to perform the EWM calculation in response to an arithmetic control signal.

8. The PIM device of claim 7 ,
wherein the arithmetic control signal is generated after a certain time elapses from a point in time when the read control signal is generated; and
wherein the certain time corresponds to a period from the point in time when the read control signal is generated until a point in time when the first input data and the second input data are outputted from the memory circuit.

9. The PIM device of claim 1 , wherein the memory circuit includes:
a first memory bank for storing the first input data;
a second memory bank for storing the second input data; and
a third memory bank for storing the result data.

10. The PIM device of claim 9 , wherein a region of the first memory bank in which the first input data are stored, a region of the second memory bank in which the second input data are stored, and a region of the third memory bank in which the result data are stored have the same row address.

11. The PIM device of claim 10 , wherein the region of the first memory bank in which the first input data are stored, the region of the second memory bank in which the second input data are stored, and the region of the third memory bank in which the result data are stored have the same column address.

12. The PIM device of claim 9 , further comprising a command/address decoder configured to sequentially generate the read control signal, the address signal, an arithmetic control signal, and the write control signal in response to an EWM command,
wherein the first memory bank and the second memory bank are configured to output the first input data and the second input data, which are stored in regions of the first and the second memory banks designated by the address signal, to the multiplier circuit in response to the read control signal; and
wherein the third memory bank is configured to store the result data into a region of the third memory bank, which is designated by the target address signal outputted from the address pipeline circuit, in response to the write control signal.

13. The PIM device of claim 1 , wherein the address pipeline circuit includes:
a plurality of address storage regions, each of which is configured to store the target address signal;
a plurality of index storage regions, each of which is configured to store an index corresponding to the target address signal;
an index generator configured to generate the index in response to the read control signal; and
an index detector configured to generate an index selection signal in response to the write control signal.

14. The PIM device of claim 13 ,
wherein the index generator is configured to count the read control signal to generate the index having the counted value of the read control signal; and
wherein the index detector is configured to count the write control signal to generate the index selection signal having the counted value of the write control signal.

15. The PIM device of claim 14 , wherein the address pipeline circuit is configured to output one of the target address signals stored in the plurality of address storage regions, which is matched with the index having the same value as the index selection signal, to the memory circuit.

Assignees

• Sk Hynix Inc

Inventors

• Son Mun Gyu
• Jeong Chun Seok

Classifications

• G06N3/063

  using electronic means · CPC title

• G06F15/7821

  Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G11C7/1039 Primary

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title