Sense amplifier, memory and method for controlling a sense amplifier

Patent metadata

Field	Value
Publication number	US-11423957-B2
Application number	US-202017441679-A
Country	US
Kind code	B2
Filing date	Dec 25, 2020
Priority date	Aug 13, 2020
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module; and a control module, electrically connected to the amplification module; wherein, in an offset compensation stage of the sense amplifier, the control module is used to configure the amplification module to comprise a diode structure, a current mirror structure, and an inverter with an input and an output connected together; and in a first amplification stage of the sense amplifier, the control module is used to configure the amplification module as an inverter. The present disclosure can realize the offset compensation of the sense amplifier, thereby improving the performance of semiconductor memories.

First claim

The invention claimed is:

1. A sense amplifier, comprising:
an amplification module; and
a control module, electrically connected to the amplification module;
wherein, in an offset compensation stage of the sense amplifier, the control module is used to configure the amplification module to comprise a diode structure, a current mirror structure, and an inverter with an input and an output connected together; and in a first amplification stage of the sense amplifier, the control module is used to configure the amplification module as the inverter.

2. The sense amplifier according to claim 1 , wherein the amplification module comprises:
a first PMOS transistor;
a second PMOS transistor, a gate of the second PMOS transistor being connected to a drain of the first PMOS transistor through a first node;
a first NMOS transistor, a gate of the first NMOS transistor being connected to a first bit line and a drain of the first NMOS transistor being connected to the first node; and
a second NMOS transistor, a gate of the second NMOS transistor being connected to a second bit line and a drain of the second NMOS transistor being connected to a drain of the second PMOS transistor through a second node;
wherein, in the offset compensation stage of the sense amplifier, the second NMOS transistor is configured as a diode structure, the first PMOS transistor and the second PMOS transistor are configured as a current mirror structure, and the first PMOS transistor and the first NMOS transistor are configured as the inverter with the input and the output connected together.

3. The sense amplifier according to claim 2 , wherein the control module comprises:
a first switch, a first terminal of the first switch being connected to the first node, and a second terminal of the first switch being connected to a gate of the first PMOS transistor;
a second switch, a first terminal of the second switch being connected to the second terminal of the first switch, and a second terminal of the second switch being connected to the second node; and
a third switch, a first terminal of the third switch being connected to the first node, and a second terminal of the third switch being connected to the first bit line; and
a fourth switch, a first terminal of the fourth switch being connected to the second bit line, and a second terminal of the fourth switch being connected to the second node;
wherein, in the offset compensation stage of the sense amplifier, the first switch, the third switch, and the fourth switch are closed, and the second switch is open.

4. The sense amplifier according to claim 3 , wherein, in the offset compensation stage of the sense amplifier, sources of the first PMOS transistor and the second PMOS transistor receive a first voltage, and sources of the first NMOS transistor and the second NMOS transistor are grounded.

5. The sense amplifier according to claim 4 , wherein, in the first amplification stage of the sense amplifier, the second PMOS transistor and the second NMOS transistor are controlled to be in a cut-off region, and the first PMOS transistor and the first NMOS transistor are configured as the inverter.

6. The sense amplifier according to claim 5 , wherein the control module further comprises:
a fifth switch, a first terminal of the fifth switch being connected to the second node, and a second terminal of the fifth switch being connected to the first bit line; and
a sixth switch, a first terminal of the sixth switch being connected to the second bit line, and a second terminal of the sixth switch being connected to the first node;
wherein, in the offset compensation stage of the sense amplifier, the fifth switch and the sixth switch are open; and in the first amplification stage of the sense amplifier, the first switch, the third switch and the fourth switch are open, and the second switch, the fifth switch, and the sixth switch are closed.

7. The sense amplifier according to claim 6 , wherein, in the first amplification stage of the sense amplifier, the source of the first PMOS transistor receives the first voltage, the source of the first NMOS transistor is grounded, the source of the second PMOS transistor and the source of the second NMOS transistor receive a second voltage;
wherein, the second voltage is lower than the first voltage.

8. The sense amplifier according to claim 7 , wherein, in a second amplification stage following the first amplification stage of the sense amplifier, the control module is used to configure the amplification module as a cross-coupled amplification structure.

9. The sense amplifier according to claim 8 , wherein, in the second amplification stage of the sense amplifier, the first switch, the third switch, and the fourth switch are open, and the second switch, the fifth switch and the sixth switch are closed.

10. The sense amplifier according to claim 9 , wherein, in the second amplification stage of the sense amplifier, the sources of the first PMOS transistor and the second PMOS transistor receive the first voltage, and the sources of the first NMOS transistor and the second NMOS transistor are grounded.

11. The sense amplifier according to claim 10 , wherein the sense amplifier further comprises:
a pre-charge module, configured to pre-charge the first bit line and the second bit line in a pre-charge stage prior to the offset compensation stage of the sense amplifier.

12. The sense amplifier according to claim 11 , wherein, in the pre-charge stage of the sense amplifier, the first switch, the second switch, the fifth switch and the sixth switch are open, and the third switch and the fourth switch are closed.

13. The sense amplifier according to claim 12 , wherein, in the pre-charge stage of the sense amplifier, the sources of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor all receive the second voltage.

14. A memory, comprising the sense amplifier according to claim 1 .

15. A method for controlling a sense amplifier, the sense amplifier comprising an amplification module and a control module, comprising:
in an offset compensation stage of the sense amplifier, configuring, by the control module, the amplification module to comprise a diode structure, a current mirror structure, and an inverter with an input and an output connected together; and
in a first amplification stage of the sense amplifier, configuring, by the control module, the amplification module as the inverter.

Assignees

• Univ Anhui
• Changxin Memory Tech Inc

Inventors

• Peng Chunyu
• Ge Junlin
• He Jun
• Ying Zhan
• Li Xin
• Cao Kanyu
• Lu Wenjuan
• Lin Zhiting
• Wu Xiulong
• Chen Junning

Classifications

• G11C7/08 Primary

  Control thereof · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title