Computer for spiking neural network with maximum aggregation

Patent metadata

Field	Value
Publication number	US-11423287-B2
Application number	US-201816634141-A
Country	US
Kind code	B2
Filing date	Jul 11, 2018
Priority date	Jul 25, 2017
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

A computer based on a spiking neural network, includes at least one maximum pooling layer. In response to an input spike received by a neuron of the maximum pooling layer, the device is configured so as to receive the address of the activated synapse. The device comprises an address comparator configured so as to compare the address of the activated synapse with a set of reference addresses. Each reference address is associated with a hardness value and with a pooling neuron. The device activates a neuron of the maximum pooling layer if the address of the activated synapse is equal to one of the reference addresses and the hardness value associated with this reference address has the highest value from among the hardness values associated with the other reference addresses of the set.

First claim

The invention claimed is:

1. A computer based on a spiking neural network, the network comprising layers of neurons, the inputs and outputs of each neuron being coded by spikes, the input spikes being received in sequence at the input of a neuron, each neuron of the network comprising a receptive field comprising at least one synapse, each synapse being associated with a synapse address, the computer being configured so as to compute, for each layer of neurons, the output value of each neuron in response to at least one input spike,
the network furthermore comprising at least one maximum pooling layer, each pooling layer comprising maximum pooling neurons, each maximum pooling neuron being able to deliver an output spike in response to the reception of an input spike on the most active synapse of its receptive field,
wherein the computer comprises a device for activating the neurons of the maximum pooling layer and in that, in response to an input spike received by a neuron of the maximum pooling layer, the device is configured so as to receive the address of the synapse associated with said received input spike, called activated synapse address, the device comprising an address comparator configured so as to compare the address of the activated synapse with a set of reference addresses, comprising at least one reference address, each reference address being associated with a hardness value and with a pooling neuron;
the device being configured so as to activate a neuron of the maximum pooling layer if the address of the activated synapse is equal to one of the reference addresses, and the hardness value associated with this reference address has the highest value from among the hardness values associated with the other reference addresses of said set.

2. The computer as claimed in claim 1 , wherein the device comprises a counter configured so as to increment the hardness value associated with a reference address of said set of reference addresses by a chosen incrementation value, if said reference address is equal to said activated synapse address, the device furthermore being configured so as to deliver an output spike value set to the value 1, in association with said reference address.

3. The computer as claimed in claim 2 , wherein the device comprises a hardness value comparator for comparing the hardness value with zero, and in that the counter is configured so as to decrement the hardness value associated with a reference address by a chosen decrementation value, if said reference address of said set of reference addresses is different from said activated synapse address and if the hardness value comparator indicates that the hardness value is strictly greater than zero.

4. The computer as claimed in claim 1 , wherein the device is configured so as to set a reference address to the value of said activated synapse address, if said reference address is different from said activated synapse address and if the hardness value is less than or equal to zero, the device furthermore being configured so as to deliver an output spike value with the value 1 associated with said reference address and set the hardness value associated with the reference address to a predefined initialization value.

5. The computer as claimed in claim 2 , wherein the device is configured so as to determine the address of the hardness value having the maximum value and to deliver, at the output of the neuron of the maximum activation layer, an output spike value corresponding to the value of the output spike associated with the reference address corresponding to said hardness value.

6. The computer as claimed in claim 1 , wherein the device comprises at least one address memory for storing said reference addresses and at least one hardness value memory for storing the hardness values associated with each reference address, each reference address in the address memory being associated with a hardness value in the hardness value memory.

7. The computer as claimed in claim 4 , wherein the device comprises at least one initialization value memory for storing at least one initialization value.

8. The computer as claimed in claim 7 , wherein the device comprises a different initialization value for each reference address and in that said initialization value memory comprises a data structure, each input of the data structure being configured so as to store an initialization value associated with a reference address.

9. The computer as claimed in claim 1 , wherein the computer is implemented in the form of a digital circuit.

10. The computer as claimed in claim 1 , wherein the computer is implemented in the form of an analog circuit.

11. A method for computing the output values of neurons in a spiking neural network comprising at least one layer of neurons, in response to at least one input spike, the inputs and outputs of each neuron being coded by spikes, the input spikes being received in sequence at input by a neuron, each neuron of the network comprising a receptive field comprising at least one synapse, each synapse being associated with a synapse address, the neural network furthermore comprising at least one maximum pooling layer, each pooling layer comprising maximum pooling neurons, each maximum pooling neuron being able to deliver an output spike in response to the reception of an input spike on the most active synapse of its receptive field,
wherein the method comprises a step of activating the neurons of the maximum pooling layer, and in that, in response to an input spike received by a neuron of the maximum pooling layer, said activation step comprises the steps of:
receiving the address of the synapse associated with said received input spike, called activated synapse address,
comparing the address of the activated synapse with a set of reference addresses, comprising at least one reference address, each reference address being associated with a hardness value and with a pooling neuron;
activating a neuron of the maximum pooling layer if the address of the activated synapse is equal to one of the reference addresses and the hardness value associated with this reference address has the highest value from among the hardness values associated with the other reference addresses of said set.

12. The method as claimed in claim 11 , wherein it comprises the steps of:
incrementing the hardness value associated with a reference address of said set of reference addresses by a chosen incrementation value, if said reference address is equal to said activated synapse address, and
delivering an output spike value set to the value 1 for said maximum pooling neuron, in association with said reference address.

13. The method as claimed in claim 11 , wherein the method comprises a step of comparing the hardness value with zero, and decrementing the hardness value associated with a reference address by a chosen decrementation value, if said reference address of said set of reference addresses is different from said activated synapse address and if the hardness value is strictly greater than zero.

14. The method as claimed in claim 11 , wherein the method comprises the steps of:
setting a reference address to the value of said activated synapse address, if said reference address is different from said activated synapse address and if the hardness value is less than or equal to zero,
delivering an output spike value set to the value 1 in association with said reference address, and
setting the hardness value associated with the reference address to a predefined initialization value.

15. The method as claimed in claim 12 , wherein the method comprises the st

Assignees

• Commissariat Energie Atomique

Inventors

• Lorrain Vincent
• Bichler Olivier

Classifications

• G06N3/045

  Combinations of networks · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/049 Primary

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G06N3/088

  Non-supervised learning, e.g. competitive learning · CPC title

• G06N3/08

  Learning methods · CPC title