Methods, devices and systems for high speed serial bus transactions

Patent metadata

Field	Value
Publication number	US-11422968-B2
Application number	US-202017030664-A
Country	US
Kind code	B2
Filing date	Sep 24, 2020
Priority date	Mar 9, 2020
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

A method can include, by operation of a host device, initiating a first transaction with at least a first device on a serial bus in synchronism with a clock, the first transaction having a predetermined response latency. The host device can initiate a second transaction on the serial bus in synchronism with the clock signal during the response latency. The first transaction and second transaction can be completed on the serial bus in synchronism with the clock. The serial bus is configured to transmit instruction data identifying transactions, target data identifying a destination for transactions, and data for transactions. Corresponding devices and systems are also disclosed.

First claim

What is claimed is:

1. A method, comprising:
by operation of a host device, initiating a first transaction with at least a first device on a serial bus in synchronism with a clock, the first transaction having a predetermined response latency;
by operation of the host device, initiating a second transaction on the serial bus in synchronism with the clock signal during the response latency;
completing the first transaction on the serial bus in synchronism with the clock; and
completing the second transaction on the serial bus in synchronism with the clock; wherein
the serial bus is configured to transmit instruction data identifying transactions, target data identifying a destination for transactions, and data for transactions;
initiating the first transaction includes the host device transmitting a first instruction on the serial bus in synchronism with the clock for receipt by the first device to access memory cells therein while activating a first select signal separate from the serial bus, and
completing the first transaction includes the host device transmitting a completion indication for receipt at the first device in synchronism with the clock to complete the access to memory cells indicated by the first instruction, the completion indication including activating the first select signal.

2. The method of claim 1 , wherein the completion indication comprises a second instruction transmitted by the host device on the serial bus for receipt by the first device.

3. The method of claim 1 , wherein:
initiating the second transaction further includes deactivating the first select signal and activating a second select signal separate from the serial bus.

4. The method of claim 1 , wherein:
initiating the first transaction includes transmitting a memory access instruction and memory address on the serial bus.

5. The method of claim 1 , further including completing the second transaction prior to the completing the first transaction.

6. The method of claim 1 , wherein:
the first transaction includes accessing a portion of a first memory device; and
the second transaction is selected from the group of: accessing a second memory device and accessing another portion of the first memory device.

7. The method of claim 1 , further including:
generating a clock signal; and
after initiating the second transaction, disabling the clock signal for a portion of the response latency.

8. A device, comprising:
at least one memory cell array;
at least one serial bus interface configured to receive instruction data, address data, and write data over a serial bus, and transmit read data over the serial bus;
a select input separate from the serial bus and configured to receive a first select signal; and
control circuits configured to split transactions, including
in response to the first select signal being activated, a first instruction being received from the serial bus, and the first select signal being subsequently deactivated, execute a first portion of a first transaction to access the at least one memory cell array indicated by the first instruction, and
in response to receiving a first completion indication on the serial bus with at least the first select signal being activated, completing the access to the at least one memory cell array of the first transaction by outputting data on the serial bus; wherein
the first completion indication is received by the device and generated by another device.

9. The device of claim 8 , wherein:
the first instruction includes a read instruction; and
the control circuits are configured to
access the at least one memory cell array to store read data in an output storage circuit in the first portion of the first transaction, and
output the read data on the serial bus to complete the first transaction.

10. The device of claim 8 , wherein:
the control circuits are configured to
in response to a second instruction received from the serial bus in synchronism with the clock signal, execute a first portion of a second transaction indicated by the second instruction, and
in response to receiving a second completion indication to completing the second transaction by outputting second data on the serial bus.

11. The device of claim 10 , wherein:
the at least one memory cell array includes a plurality of banks;
the first portion of the first operation accesses a first bank; and
the first portion of the second operation accesses a second bank.

12. The device of claim 8 , wherein the completion indication further comprises any selected from the group of: a completion instruction received on the serial bus from the other device, a signal separate from the serial bus generated by the device, and a signal separate from the serial bus generated by the other device.

13. The device of claim 8 , wherein the at least one serial bus interface is configured to receive and transmit data in synchronism with consecutive rising and falling edges of a clock signal.

14. The device of claim 8 , wherein:
the control circuits are configured to
in response to a predetermined instruction received from the serial bus in synchronism with the clock, return parameter information indicating the device can execute split transactions.

15. The device of claim 8 , wherein the at least one memory array comprises at least one array of NOR flash memory cells.

16. A system, comprising:
a host device comprising
at least one serial bus interface coupled to a serial bus and configured to transmit instruction data, address data, and write data over a serial bus, and receive data over the serial bus; and
controller circuits configured to execute pipelined split transactions on the serial bus, including
initiating a first transaction with at least one peripheral device on the serial bus in synchronism with a clock, the first transaction having a predetermined response latency,
initiating a second transaction with the at least one peripheral device on the serial bus in synchronism with the clock during the response latency,
completing the first transaction on the serial bus in synchronism with the clock, and
completing the second transaction on the serial bus in synchronism with the clock; wherein

initiating the first transaction includes the host device transmitting a first instruction on the serial bus directly to the at least one peripheral device to access memory cells therein while activating a first select signal separate from the serial bus, and
completing the first transaction includes the host device transmitting a completion indication on the serial bus directly to the at least one peripheral device to complete the access to memory cells indicated by the first instruction while activating the first select signal.

17. The system of claim 16 , wherein the completion indication further includes a signal separate from the serial bus.

18. The system of claim 16 , further including:
the at least one peripheral device coupled to the serial bus and configured to
execute a first portion of a first operation in response to initiating the first transaction, and
complete the first operation in response to an input from the host device to complete the first transaction.

19. The system of claim 18 , further including:
a second peripheral device coupled to the serial bus and configured to
execute a first portion of a second operation in response initiating the second transaction, and
complete the second operation in response to an input from the host device to complete the second transaction.

Assignees

• Infineon Technologies LLC

Inventors

• Zitlaw Clifford
• Rosner Stephan

Classifications

• G06F2213/0008

  High speed serial bus, e.g. Fiber channel · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/161

  with latency improvement · CPC title

• G06F9/38

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title