Address translation technologies

Patent metadata

Field	Value
Publication number	US-11422944-B2
Application number	US-202016989667-A
Country	US
Kind code	B2
Filing date	Aug 10, 2020
Priority date	Aug 10, 2020
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

Examples herein relate to a system that includes a first memory device; a second memory device; and an input-output memory management unit (IOMMU). The IOMMU can search for a virtual-to-physical address translation entry in a first table for a received virtual address and based on a virtual-to-physical address translation entry for the received virtual address not being present in the first table, search a second table for a virtual-to-physical address translation entry for the received virtual address, wherein the first table is stored in the first memory device and the second table is stored in the second memory device. In some examples, based on a virtual-to-physical address translation entry for the received virtual address not being present in the second table, a page table walk is performed to determine a virtual-to-physical address translation for the received virtual address. In some examples, the first table includes an IO translation lookaside buffer (IOTLB).

First claim

What is claimed is:

1. An apparatus comprising:
a first memory device;
a second memory device; and
an input-output memory management unit (IOMMU) to:
search for a virtual-to-physical address translation entry in a first table for a received virtual address;
based on a virtual-to-physical address translation entry for the received virtual address not being present in the first table, search a second table for a virtual-to-physical address translation entry for the received virtual address, wherein the first table is stored in the first memory device, the second table is stored in the second memory device; and
limit a number of entries permitted to be stored in the first table for a process identifier based on a priority level associated with the process identifier.

2. The apparatus of claim 1 , wherein the IOMMU is to:
based on a virtual-to-physical address translation entry for the received virtual address not being present in the second table, perform a page table walk to determine a virtual-to-physical address translation for the received virtual address.

3. The apparatus of claim 1 , wherein the first table comprises an input-output (IO) translation lookaside buffer (IOTLB).

4. The apparatus of claim 1 , wherein the IOMMU is to:
provide the virtual-to-physical address translation entry for the received virtual address for storage in the first table;
based on the first table being full, invalidate an entry in the first table and store the virtual-to-physical address translation entry for the received virtual address using the invalidated entry in the first table; and
store the invalidated entry in the second table.

5. The apparatus of claim 4 , wherein the IOMMU is to limit a number of entries permitted to be stored in the first table and the second table for a source of the received virtual address based on a priority level of a source of the received virtual address.

6. The apparatus of claim 1 , wherein the IOMMU is to:
receive a process identifier comprising a Process Address Space ID (PASID);
determine a memory address of the second table based at least on the PASID; and
access the second table based on the memory address.

7. The apparatus of claim 1 , wherein the IOMMU is to:
receive a memory access request associated with the received virtual address and process identifier from a device, application, or virtual machine.

8. The apparatus of claim 1 , comprising one or more of: a server, rack, or data center, the one or more of a server, rack, or data center to write data to a memory or storage device using the virtual-to-physical address translation or read data from the memory or storage device using the virtual-to-physical address translation.

9. A computer-implemented method comprising:
receiving a virtual address with a memory access request;
searching, by an input-output memory management unit (IOMMU), for a virtual-to-physical address translation entry in a first table for the received virtual address;
based on a virtual-to-physical address translation entry for the received virtual address not being present in the first table, searching, by the IOMMU, a second table for a virtual-to-physical address translation entry for the received virtual address, wherein the first table is stored in a different memory device than a memory device that stores the second table; and
limiting, by the IOMMU, a number of entries permitted to be stored in the first table for a process identifier based on a priority level associated with the process identifier.

10. The method of claim 9 , comprising:
based on a virtual-to-physical address translation entry for the received virtual address not being present in the second table, performing, by the IOMMU, a page table walk to determine a virtual-to-physical address translation for the received virtual address.

11. The method of claim 9 , wherein the first table comprises an IO translation lookaside buffer (IOTLB).

12. The method of claim 9 , wherein the second table is stored in a memory device that is accessible to the IOMMU.

13. The method of claim 9 , comprising:
providing the virtual-to-physical address translation entry for the received virtual address for inclusion in the first table;
based on the first table being full, invalidating an entry in the first table and storing the virtual-to-physical address translation entry for the received virtual address using the invalidated entry in the first table; and
storing a virtual-to-physical address translation for the invalidated entry in the second table.

14. The method of claim 13 , comprising:
limiting a number of entries permitted to be stored in the first table and the second table for a source of the received virtual address based on a priority level of a source of the received virtual address.

15. The method of claim 9 , comprising:
receiving a process identifier with the memory access request;
determining a memory address of the second table based at least on the process identifier; and
accessing the second table based on the determined memory address.

16. The method of claim 9 , comprising:
receiving the memory access request from a device, application, or virtual machine.

17. A non-transitory computer-readable medium comprising instructions stored-thereon, that if executed by one or more processors of an input-output memory management unit (IOMMU), cause the one or more processors to:
search for a virtual-to-physical address translation entry in a first table for a received virtual address;
based on a virtual-to-physical address translation entry for the received virtual address not being present in the first table, search a second table for a virtual-to-physical address translation entry for the received virtual address, wherein the first table is stored in a first memory device and the second table is stored in a second memory device; and
limit a number of entries permitted to be stored in the first table for a process identifier based on a priority level associated with the process identifier.

18. The computer-readable medium of claim 17 , wherein the received virtual address is received from at least one device communicatively coupled to the IOMMU using a Peripheral Component Interconnect express (PCIe) compatible interface.

19. The computer-readable medium of claim 18 , wherein the at least one device comprises one or more of: a network interface card, graphics processor, video encoder or decoder, or accelerator device.

20. The computer-readable medium comprising instructions of claim 17 , wherein a potential number of address translation entries in the second table is to exceed a maximum number of permitted address translation entries in the first table.

Assignees

• Intel Corp

Inventors

• Guo Kaijie
• Li Weigang
• Wang Junyuan
• Ma Liang
• Lukoshkov Maksim
• Huo yao

Classifications

• G06F12/1081

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/683

  Invalidation · CPC title