Restartable cache write-back and invalidation

Patent metadata

Field	Value
Publication number	US-11422811-B2
Application number	US-202017098129-A
Country	US
Kind code	B2
Filing date	Nov 13, 2020
Priority date	Dec 20, 2018
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

A processor includes a global register to store a value of an interrupted block count. A processor core, communicably coupled to the global register, may, upon execution of an instruction to flush blocks of a cache that are associated with a security domain: flush the blocks of the cache sequentially according to a flush loop of the cache; and in response to detection of a system interrupt: store a value of a current cache block count to the global register as the interrupted block count; and stop execution of the instruction to pause the flush of the blocks of the cache. After handling of the interrupt, the instruction may be called again to restart the flush of the cache.

First claim

What is claimed is:

1. A processor comprising:
a secure data store to store an indicator of an interrupted block count; and
a processor core communicably coupled to the secure data store, the processor core to, upon execution of an instruction to flush blocks of a cache associated with a security domain:
flush the blocks of the cache sequentially according to a flush loop of the cache;
during each iteration of the flush loop, store an indicator of a current cache block count in the secure data store; and
in response to detection of a system interrupt:
stop execution of the instruction to pause the flush of the blocks of the cache; and
in response to the pause, the indicator of the current cache block count in the secure data store is the indicator of the interrupt block count.

2. The processor of claim 1 , wherein the security domain comprises a first trust domain and a virtual machine manager (VMM) calls for execution of the instruction to flush the blocks of the cache, wherein the processor core is to execute the VMM, which is to:
detect that the first trust domain, which owns a host key identifier (HKID) to be reclaimed for assignment to a second trust domain, is in a quiesced state; and
call for execution of the instruction, which identifies the HKID, to flush the blocks of the cache that are associated with the first trust domain.

3. The processor of claim 2 , wherein the processor core is further to:
tag that the flush of the cache has started; and
in response to the system interrupt, set an interrupt flag in a flag register that indicates the flush of the cache is interrupted.

4. The processor of claim 3 , wherein the processor core is further to execute the VMM, which is to:
detect the interrupt flag is set within the flag register;
handle the system interrupt; and
reissue a call for execution of the instruction to complete flush of the cache.

5. The processor of claim 4 , wherein the processor core is further to:
retrieve the indicator of the interrupted block count stored in the secure data store; and
resume execution of the instruction to resume the flush of the cache from a location within the cache identified by the indicator of the interrupted block count.

6. The processor of claim 4 , wherein the processor core is further to, in response to completion of the flush:
set a completion flag in the flag register to indicate successful cache flush completion; and
reset the indicator of the value of the interrupt block count in the secure data store.

7. The processor of claim 1 , wherein the indicator of the interrupted block count comprises an iteration number of the flush loop at which the system interrupt occurs, and wherein the cache comprises all caches available to the processor core for caching.

8. A system comprising:
a cache to store data read from a memory device;
a secure data store to store an indicator of an interrupted block count; and
a processor comprising a processor core, the processor core, upon execution of an instruction to flush blocks of the cache associated with a first trust domain, to:
flush the blocks of the cache sequentially according to a flush loop of the cache;
store an indicator of a current cache block count, at each iteration of the flush loop, into the secure data store;
detect a system interrupt;
stop execution of the instruction to pause the flush of the cache in response to the system interrupt; and
in response to the pause, the indicator of the current cache block count in the secure data store is the indicator of the interrupt block count.

9. The system of claim 8 , wherein the secure data store comprises protected hardware.

10. The system of claim 8 , wherein the processor is further to:
tag, within key identifier (ID) tracker logic, that the flush of the cache has started; and
in response to the system interrupt, set an interrupt flag in a flag register that indicates the flush of the cache is interrupted.

11. The system of claim 10 , wherein the processor core is further to execute a virtual machine manager (VMM), which is to:
detect the interrupt flag is set within the flag register; handle the system interrupt; and
reissue a call for execution of the instruction to complete flush of the cache.

12. The system of claim 11 , wherein the processor is further to:
retrieve the interrupted block count stored in the secure data store; and
resume execution of the instruction to resume the flush of the cache from a location within the cache identified by the indicator of the interrupted block count.

13. The system of claim 8 , wherein the processor core is further to execute a virtual machine manager (VMM) to:
detect that the first trust domain, which owns a host key identifier (HKID) to be reclaimed for assignment to a second trust domain, is in a quiesced state; and
call for execution of an instruction, which identifies the HKID, to flush the blocks of the cache that are associated with the first trust domain;
and wherein the processor is further to tag the HKID as being in a reclaim state.

14. The system of claim 8 , wherein the indicator of the interrupted block count comprises an iteration number of the flush loop at which the system interrupt occurs.

15. A method comprising:
executing, by a processor, an instruction to flush blocks of a cache associated with a first trust domain;
initializing, by the processor during execution of the instruction, an indicator of a current cache block count; and
iteratively, by the processor, over a flush loop of the cache:
flushing a cache block associated with the indicator of the current cache block count;
incrementing the indicator of the current cache block count;
determining whether the indicator of the current cache block count corresponds to a total of the cache blocks of the cache;
detecting whether an interrupt is pending; and
in response to detecting a system interrupt is pending:
stopping execution of the instruction to pause the flush of the cache; and
storing the indicator of the current cache block count into protected hardware storage as an interrupted block count.

16. The method of claim 15 , wherein initializing the indicator of the current cache block count comprises setting the indicator of the current cache block count to be an indicator of the interrupted block count upon beginning execution of the instruction.

17. The method of claim 15 , wherein, in response to the indicator for the current cache block count being equal to the total cache blocks:
setting a completion flag in a flag register; and setting the interrupt block count to a zero value.

18. The method of claim 15 , further comprising:
detecting, by a virtual machine monitor (VMM) running on the processor, prior to executing the instruction, that the first trust domain, which owns a host key identifier (HKID) to be reclaimed for assignment to a second trust domain, is in a quiesced state;
calling by the VMM prior to executing the instruction, for execution of the instruction, which identifies the HKID, to flush blocks of the cache that are associated with the first trust domain;
setting an interrupt flag in a flag register that indicates the flush of the cache is interrupted;
detecting, by the VMM, the interrupt flag is set within the flag register; handling, by the VMM, the system interrupt; and
reissuing, by the VMM, a call for execution of the instruction to complete flush of the cache.

19. The method of claim 18 , further comprising:
retrieving, by the processor hardware, the int

Assignees

• Intel Corp

Inventors

• Gerzon Gideon
• Caspi Dror
• Aharon Arie
• Ouziel Ido

Classifications

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title

• G06F12/0842

  for multiprocessing or multitasking · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title