Thin film transistor and method for manufacturing same, array substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-11417769-B2
Application number	US-201716063743-A
Country	US
Kind code	B2
Filing date	Dec 12, 2017
Priority date	May 11, 2017
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

Provided are a thin film transistor and method for manufacturing the same, array substrate, display panel and display device. The thin film transistor includes: a gate pattern, a gate insulating layer, an active layer pattern, a source pattern and a drain pattern sequentially stacked. At least one of a surface of the source pattern facing the gate insulating layer, a surface of the drain pattern facing the gate insulating layer, and a surface of the gate pattern facing the gate insulating layer is a target surface which can diffusely reflect lights entering the target surface, to prevent part of the lights from entering the active layer pattern. The display device solves the problem of volt-ampere characteristic curve of the active layer pattern being deflected and a normal operation of the thin film transistor being affected, thereby weakening the influence of lights on the normal operation of the thin film transistor.

First claim

What is claimed is:

1. A thin film transistor, comprising a gate pattern, a gate insulating layer, an active layer pattern, a source pattern and a drain pattern that are sequentially stacked, a material of the active layer pattern is a metal oxide semiconductor, the source pattern and the drain pattern are spaced apart and are both connected to the active layer pattern, orthographic projections of the gate pattern, the active layer pattern and the source pattern onto the gate insulating layer have an overlapping area, orthographic projections of the gate pattern, the active layer pattern and the drain pattern onto the gate insulating layer have an overlapping area; wherein
the gate pattern comprises a first area and a second area, an orthographic projections of the first area onto the gate insulating layer and the orthographic projection of the active layer pattern onto the gate insulating layer coincide, and the first area is enclosed by the second area;
the source pattern comprises a first conductive metal oxide structure disposed in a surface of the source pattern facing the gate insulating layer, and the first conductive metal oxide structure and the active layer pattern are both disposed on the gate insulating layer and are spaced apart from each other,
the drain pattern comprises a second conductive metal oxide structure disposed in a surface of the drain pattern facing the gate insulating layer, and the second conductive metal oxide structure and the active layer pattern are both disposed on the gate insulating layer and are spaced apart from each other;
the active layer pattern is rectangular, the first conductive metal oxide structure and the second conductive metal oxide structure are both U-shaped, and are respectively located on opposite sides of the active layer pattern, each surrounding the active layer pattern;
a surface of the first conductive metal oxide structure facing the gate insulating layer and a surface of the second conductive metal oxide structure facing the gate insulating layer are both rough surfaces, the rough surface surfaces are capable of diffusely reflecting light arriving at the rough surfaces, so as to reduce light entering the active layer pattern.

2. The thin film transistor according to claim 1 , wherein the gate pattern comprises a third electrode main pattern, and a third target pattern provided on a side of the third electrode main pattern, the gate insulating layer is provided on a side of the third target pattern away from the third electrode main pattern, and a surface of the third target pattern away from the third electrode main pattern is a rough surface.

3. The thin film transistor according to claim 1 , wherein the gate pattern comprises a third electrode main pattern, and a third target pattern provided on a side of the third electrode main pattern, the gate insulating layer is provided on a side of the third target pattern away from the third electrode main pattern, and a surface of the third target pattern away from the third electrode main pattern is a rough surface.

4. The thin film transistor according to claim 1 , further comprising a passivation layer, wherein a pixel electrode is connected with the drain pattern through a via hole in the passivation layer.

5. The thin film transistor according to claim 1 , the metal oxide semiconductor is indium gallium zinc oxide.

6. The thin film transistor according to claim 1 , wherein the source pattern further comprises a first electrode main pattern, disposed on a side of the first conductive metal oxide away from the gate pattern;
the drain pattern further comprises a second electrode main pattern, disposed on a side of the second conductive metal oxide away from the gate pattern; and
the first electrode main pattern and the second electrode main pattern are both connected to the active layer pattern.

7. An array substrate, comprising a thin film transistor, wherein the thin film transistor comprises a gate pattern, a gate insulating layer, an active layer pattern, a source pattern and a drain pattern that are sequentially stacked, a material of the active layer pattern is a metal oxide semiconductor, the source pattern and the drain pattern are spaced apart and are both connected to the active layer pattern, orthographic projections of the gate pattern, the active layer pattern and the source pattern onto the gate insulating layer have an overlapping area, orthographic projections of the gate pattern, the active layer pattern and the drain pattern onto the gate insulating layer have an overlapping area; wherein
the gate pattern comprises a first area and a second area, an orthographic projections of the first area onto the gate insulating layer and the orthographic projection of the active layer pattern onto the gate insulating layer coincide, and the first area is enclosed by the second area;
the source pattern comprises a first conductive metal oxide structure disposed in a surface of the source pattern facing the gate insulating layer, and the first conductive metal oxide structure and the active layer pattern are both disposed on the gate insulating layer and are spaced apart from each other;
the drain pattern comprises a second conductive metal oxide structure disposed in a surface of the drain pattern facing the gate insulating layer, and the second conductive metal oxide structure and the active layer pattern are both disposed on the gate insulating layer and are spaced apart from each other;
the active layer pattern is rectangular, the first conductive metal oxide structure and the second conductive metal oxide structure are both U-shaped, and are respectively located on opposite sides of the active layer pattern, each surrounding the active layer pattern;
a surface of the first conductive metal oxide structure facing the gate insulating layer and a surface of the second conductive metal oxide structure facing the gate insulating layer are both rough surfaces, the rough surface are capable of diffusely reflecting light arriving at the rough surfaces, so as to reduce light entering the active layer pattern.

8. A display panel, comprising the array substrate according to claim 7 , wherein the display panel is a liquid crystal display panel or an organic light emitting diode display panel.

9. The array substrate according to claim 7 , wherein the gate pattern comprises a third electrode main pattern, and a third target pattern provided on a side of the third electrode main pattern, the gate insulating layer is provided on a side of the third target pattern away from the third electrode main pattern, and a surface of the third target pattern away from the third electrode main pattern is a rough surface.

10. The array substrate according to claim 7 , wherein the gate pattern comprises a third electrode main pattern, and a third target pattern provided on a side of the third electrode main pattern, the gate insulating layer is provided on a side of the third target pattern away from the third electrode main pattern, and a surface of the third target pattern away from the third electrode main pattern is a rough surface.

11. The array substrate according to claim 7 , wherein the thin film transistor further comprises a passivation layer, and a pixel electrode is connected with the drain pattern through a via hole in the passivation layer.

12. The array substrate according to claim 7 , wherein the source pattern further comprises a first electrode main pattern, disposed on a side of the first conductive metal oxide away from the gate pattern;
the drain pattern further comprises a second electrode main pattern, disposed on a side of the second conductive metal oxide away from the gat

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Cao Binbin
• Wang Chao
• Sun Lin

Classifications

• H10P50/69

  using masks for semiconductor materials · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P95/70

  Chemical treatments · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/20 Primary

  Dry etching; Plasma etching; Reactive-ion etching · CPC title