Quantum dot devices with fine-pitched gates

Patent metadata

Field	Value
Publication number	US-11417765-B2
Application number	US-201816017942-A
Country	US
Kind code	B2
Filing date	Jun 25, 2018
Priority date	Jun 25, 2018
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric layer; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric layer, and the second gate dielectric layer extends over the first gate.

First claim

The invention claimed is:

1. A quantum dot device, comprising:
a base;
a fin extending away from the base, wherein the fin includes a quantum well stack;
a first gate at least partially above the fin, wherein the first gate includes a first gate metal and a first gate dielectric, and the first gate dielectric has a horizontal portion and a vertical portion; and
a second gate at least partially above the fin, wherein the second gate includes a second gate metal and a second gate dielectric, and the second gate dielectric has a horizontal portion and a vertical portion;
wherein the vertical portion of the first gate dielectric is in contact with the vertical portion of the second gate dielectric, and wherein a spacing between the first gate metal and the second gate metal is between 3 nanometers and 10 nanometers.

2. The quantum dot device of claim 1 , wherein the first gate dielectric has a U-shaped cross-section and the vertical portion of the first gate dielectric is part of the U-shaped cross-section.

3. The quantum dot device of claim 2 , wherein the second gate dielectric extends over the first gate.

4. The quantum dot device of claim 3 , wherein a height of the second gate is greater than a height of the first gate.

5. The quantum dot device of claim 1 , wherein the second gate dielectric extends over the first gate.

6. The quantum dot device of claim 1 , wherein a height of the second gate is greater than a height of the first gate.

7. The quantum dot device of claim 1 , wherein the quantum well stack includes an isotopically purified material.

8. The quantum dot device of claim 1 , wherein:
the first gate metal and the second gate metal are absent on sidewalls of the fin.

9. The quantum dot device of claim 1 , wherein the quantum well stack includes a quantum well layer, and wherein the quantum well layer is in the fin, extends along a length of the fin, and is parallel to the base.

10. The quantum dot device of claim 1 , wherein:
the quantum well stack includes a quantum well layer and either a buffer layer or an insulating layer,
when the quantum well stack includes the buffer layer, the buffer layer is between the base and the quantum well layer, and
when the quantum well stack includes the insulating layer, the insulating layer is between the base and the quantum well layer.

11. The quantum dot device of claim 1 , further comprising a magnet line, wherein the magnet line is to perform one or more of:
generate magnetic fields to influence spin states of one or more of quantum dots formed in the fin during operation of the quantum dot device,
reset or scramble nuclear or quantum dot spins during operation of the quantum dot device,
initialize a charge carrier in a quantum dot in a particular spin state during operation of the quantum dot device, and
couple a spin of a qubit.

12. The quantum dot device of claim 1 , wherein:
the quantum dot device is a quantum computing device,
the quantum computing device includes a quantum processing device and a non-quantum processing device,
the quantum processing device includes the base, the fin, the first gate, and the second gate, and
the non-quantum processing device is coupled to the quantum processing device and is to control voltages applied to the first gate and the second gate.

13. The quantum computing device of claim 12 , further comprising:
a memory device to store data generated by quantum dots formed in the quantum well stack during operation of the quantum processing device.

14. The quantum computing device of claim 13 , wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

15. The quantum computing device of claim 12 , further comprising:
a cooling apparatus to maintain a temperature of the quantum processing device below 5 Kelvin.

16. A quantum dot device, comprising:
a base;
a fin extending away from the base, wherein the fin includes a quantum well stack;
a first gate at least partially above the fin, wherein the first gate includes a first gate metal and a first gate dielectric layer; and
a second gate at least partially above the fin, wherein the second gate includes a second gate metal and a second gate dielectric layer, the second gate dielectric layer extends over the first gate, and a spacing between the first gate metal and the second gate metal is between 3 nanometers and 10 nanometers.

17. The quantum dot device of claim 16 , wherein the first gate dielectric layer includes hafnium.

18. The quantum dot device of claim 16 , wherein the first gate metal and the second gate metal have different material structures.

19. The quantum dot device of claim 16 , further comprising:
a third gate above the quantum well stack, wherein the third gate includes a third gate metal and a third gate dielectric layer, the first gate is between the second gate and the third gate, and the second gate dielectric layer and the third gate dielectric layer are provided by a common, continuous layer of dielectric material.

20. The quantum dot device of claim 16 , further comprising:
a barrier material between a vertical portion of the first gate dielectric layer and a vertical portion of the second gate dielectric layer.

21. The quantum dot device of claim 16 , wherein:
the first gate metal and the second gate metal are absent on sidewalls of the fin.

22. The quantum dot device of claim 16 , wherein the quantum well stack includes a quantum well layer, and wherein the quantum well layer is in the fin, extends along a length of the fin, and is parallel to the base.

23. The quantum dot device of claim 16 , wherein:
the quantum well stack includes a quantum well layer and either a buffer layer or an insulating layer,
when the quantum well stack includes the buffer layer, the buffer layer is between the base and the quantum well layer, and
when the quantum well stack includes the insulating layer, the insulating layer is between the base and the quantum well layer.

24. The quantum dot device of claim 16 , wherein:
the quantum dot device is a quantum computing device,
the quantum computing device includes a quantum processing device, a non-quantum processing device, and a memory device,
the quantum processing device includes the base, the fin, the first gate, and the second gate,
the non-quantum processing device is coupled to the quantum processing device and is to control voltages applied to the first gate and the second gate, and
the memory device is to store data generated by quantum dots formed in the quantum well stack during operation of the quantum processing device.

25. The quantum computing device of claim 24 , further comprising:
a cooling apparatus to maintain a temperature of the quantum processing device below 5 Kelvin.

Assignees

• Intel Corp

Inventors

• Thomas Nicole K
• Pillarisetty Ravi
• Singh Kanwaljit
• George Hubert C
• Michalak David J
• Lampert Lester
• Yoscovits Zachary R
• Caudillo Roman
• Roberts Jeanette M
• Clarke James S

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10D48/3835

  Semiconductor qubit devices comprising a plurality of quantum mechanically interacting semiconductor quantum dots, e.g. Loss-DiVincenzo spin qubits · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title