Semiconductor wafer of monocrystalline silicon and method of producing the semiconductor wafer

US11417733B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11417733-B2
Application numberUS-201816636352-A
CountryUS
Kind codeB2
Filing dateJul 19, 2018
Priority dateAug 4, 2017
Publication dateAug 16, 2022
Grant dateAug 16, 2022

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Abstract

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Epitaxially coated semiconductor wafers of monocrystalline silicon comprise a p+-doped substrate wafer and a p-doped epitaxial layer of monocrystalline silicon which covers an upper side face of the substrate wafer;an oxygen concentration of the substrate wafer of not less than 5.3×1017 atoms/cm3 and not more than 6.0×1017 atoms/cm3;a resistivity of the substrate wafer of not less than 5 mΩcm and not more than 10 mΩcm; andthe potential of the substrate wafer to form BMDs as a result of a heat treatment of the epitaxially coated semiconductor wafer, where a high density of BMDs has a maximum close to the surface of the substrate wafer.

First claim

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The invention claimed is: 1. An epitaxially coated semiconductor wafer of monocrystalline silicon, comprising: a p + -doped substrate wafer; a p-doped epitaxial layer of monocrystalline silicon which covers an upper face of the substrate wafer; an oxygen concentration of the substrate wafer of not less than 5.3×10 17 atoms/cm 3 and not more than 6.0×10 17 atoms/cm 3 ; a resistivity of the substrate wafer of not less than 5 mΩcm and not more than 10 mΩcm; and a potential of the substrate wafer to form BMDs (bulk microdefects) as a result of a two-stage heat treatment of the epitaxially coated semiconductor wafer, where the density of BMDs has a maximum of not less than 2×10 10 /cm 3 , the distance of the maximum from a front side of the epitaxially coated semiconductor wafer is not greater than 20 μm, and the ratio of the densities of BMDs at a distance of 20 μm and at a distance of 60 μm from the front side of the epitaxially coated semiconductor wafer is not less than 5, and the two-stage heat treatment is effected at 850° C. over a period of one hour in oxygen and at 1000° C. over a period of one hour in oxygen. 2. The epitaxially coated semiconductor wafer of claim 1 , wherein the epitaxial layer has a thickness of not less than 1 μm and not more than 5 μm. 3. The epitaxially coated semiconductor water of claim 1 , having a denuded zone having a thickness of not less than 3 μm and not more than 7 μm. 4. The epitaxially coated semiconductor wafer of claim 2 , having a denuded tone having a thickness of not less than 3 μm and not more than 7 μm.

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What does patent US11417733B2 cover?
Epitaxially coated semiconductor wafers of monocrystalline silicon comprise a p+-doped substrate wafer and a p-doped epitaxial layer of monocrystalline silicon which covers an upper side face of the substrate wafer;an oxygen concentration of the substrate wafer of not less than 5.3×1017 atoms/cm3 and not more than 6.0×1017 atoms/cm3;a resistivity of the substrate wafer of not less than 5 mΩcm a…
Who is the assignee on this patent?
Siltronic Ag
What technology area does this patent fall under?
Primary CPC classification H10P14/3411. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 16 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).