Nonvolatile memory device of three-dimensional structure including resistance change element

Patent metadata

Field	Value
Publication number	US-11417707-B2
Application number	US-202016983929-A
Country	US
Kind code	B2
Filing date	Aug 3, 2020
Priority date	Mar 19, 2020
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

A nonvolatile memory device according to an embodiment includes a substrate and a gate structure disposed on the substrate. The gate structure includes at least one gate electrode layer and at least one interlayer insulation layer that are alternately stacked. In addition, the nonvolatile memory device includes a hole pattern penetrating the gate structure on the substrate, and a gate insulation layer, a first ion retention layer, a second ion retention layer, and a channel layer sequentially covering a sidewall surface of the gate electrode layer in the hole pattern. The first and second ion retention layers comprise ions exchangeable with each other.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a substrate;
a gate structure disposed on the substrate, the gate structure including at least one gate electrode layer and at least one interlayer insulation layer that are alternately stacked;
a hole pattern penetrating the gate structure on the substrate; and
a gate insulation layer, a first ion retention layer, a second ion retention layer, and a channel layer sequentially covering a sidewall surface of the gate electrode layer in the hole pattern,
wherein the first and second ion retention layers comprise ions exchangeable with each other.

2. The nonvolatile memory device of claim 1 , further comprising:
a channel lower contact layer disposed on the substrate, contacting a first end of the channel layer; and
a channel upper contact layer contacting a second, opposite end of the channel layer,
wherein the channel lower contact layer and the channel upper contact layer are electrically connected to a source electrode and a drain electrode, respectively.

3. The nonvolatile memory device of claim 1 , wherein the first and second ion retention layers comprise metal cations exchangeable with each other.

4. The nonvolatile memory device of claim 3 , wherein the first ion retention layer provides metal cations to the second ion retention layer when a predetermined positive voltage is applied to the gate electrode layer.

5. The nonvolatile memory device of claim 4 , wherein, after the positive voltage applied to the gate electrode layer is removed, the second ion retention layer stores, in a non-volatile manner, an electrical resistance that is decreased based on an increased amount of the metal cations.

6. The nonvolatile memory device of claim 3 , wherein the second ion retention layer provides metal cations to the first ion retention layer when a predetermined negative voltage is applied to the gate electrode layer.

7. The nonvolatile memory device of claim 6 , wherein, after the negative voltage applied to the gate electrode layer is removed, the second ion retention layer stores, in a non-volatile manner, an electrical resistance that is increased based on a decreased amount of the metal cations.

8. The nonvolatile memory device of claim 1 , wherein each of the first and second ion retention layers comprises at least one selected from lithium-based oxide, transition metal oxide, and perovskite-based materials.

9. The nonvolatile memory device of claim 1 , wherein the second ion retention layer has a multi-level electrical resistance based on an amount of retained ions.

10. The nonvolatile memory device of claim 1 , wherein the interlayer insulation layer extends toward a center of the hole pattern to be disposed to contact the channel layer.

11. The nonvolatile memory device of claim 1 wherein the second ion retention layer is disposed to contact the channel layer.

12. A nonvolatile memory device comprising:
a substrate;
a gate structure disposed on the substrate, the gate structure including at least one gate electrode layer and at least one interlayer insulation layer that are alternately stacked along a first direction perpendicular to an upper surface of the substrate, wherein the gate structure extends in a second direction perpendicular to the first direction; and
a gate insulation layer, a first ion retention layer, a second ion retention layer, and a channel layer sequentially covering a sidewall surface of the gate electrode layer on the substrate,
wherein the first and second ion retention layers comprise ions exchangeable with each other.

13. The nonvolatile memory device of claim 12 , wherein the first and second ion retention layers comprise metal cations exchangeable with each other.

14. The nonvolatile memory device of claim 12 , wherein each of the first and second ion retention layers comprises at least one selected from lithium-based oxide, transition metal oxide, and perovskite-based materials.

15. The nonvolatile memory device of claim 12 , further comprising:
a channel lower contact layer disposed on the substrate, contacting a first end of the channel layer; and
a channel upper contact layer contacting a second, opposite end of the channel layer,
wherein the channel lower contact layer and the channel upper contact layer are electrically connected to a source electrode and a drain electrode, respectively.

16. The nonvolatile memory device of claim 12 , wherein the second ion retention layer has a multi-level electrical resistance based on an amount of retained ions.

17. The nonvolatile memory device of claim 16 , wherein the amount of retained ions is controlled by a voltage applied to the gate electrode layer.

18. The nonvolatile memory device of claim 12 , further comprising a plurality of cell insulation structures disposed on the substrate and spaced apart from each other in the second direction,
wherein the plurality of cell insulation structures extend in the first direction on the substrate and extend in a third direction perpendicular to the first and second directions and separate the first ion retention layer, the second ion retention layer and the channel layer with respect to the second direction.

19. The nonvolatile memory device of claim 12 , wherein the interlayer insulation layer extends in a third direction perpendicular to the first and second directions to be disposed to contact the channel layer.

20. The nonvolatile memory device of claim 12 , wherein the second ion retention layer is disposed to contact the channel layer.

Assignees

• Sk Hynix Inc

Inventors

• Han Jae Hyun

Classifications

• H10D48/366 Primary

  Multistable devices; Devices having two or more distinct operating states · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H01L45/1233

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L27/2481 Primary

  Electricity · mapped topic