Control surface access using flat memory mapping

Patent metadata

Field	Value
Publication number	US-11416402-B2
Application number	US-202017068742-A
Country	US
Kind code	B2
Filing date	Oct 12, 2020
Priority date	Mar 27, 2019
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. An apparatus, comprising:
a processor to:
allocate a first memory space in a physical memory for data for a graphics workload, the first memory space comprising a first plurality of addressable physical memory locations;
allocate a second memory space in the physical memory for compression metadata relating to the data for the graphics workload, the compression metadata defining one or more elements of a compression technique used to compress the data for the graphics workload, the second memory space comprising a second plurality of addressable physical memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space;
configure a direct memory mapping between the first plurality of addressable physical memory locations and the second plurality of addressable physical memory locations; and
repack the compression metadata in the second memory space using a hash function that relates a first physical addressable memory location in the second memory space to a second physical addressable memory location in the second memory space.

2. The apparatus of claim 1 , wherein the predetermined ratio of the amount of memory allocated to the first memory space to the amount of memory in the second memory space is 256:1.

3. The apparatus of claim 1 , the processor to:
receive a memory access request for the data for the graphics workload, the memory access request comprising a first memory address in the first memory space;
determine, from the first physical memory address, a second physical memory address in the second memory space; and
retrieve, from the second memory address, the compression metadata stored therein.

4. The apparatus of claim 3 , the processor to:
retrieve, from the first physical memory address, the data for the graphics workload; and
use the compression metadata to facilitate decompression of the data for the graphics workload in the first physical memory address in the first memory space.

5. The apparatus of claim 1 , the processor to:
receive a memory access request for the data for the graphics workload, the data access request comprising a first memory address in the first physical memory space;
determine, from the first memory address and the hash function, a second memory address in the second physical memory space; and
retrieve, from the second physical memory address, the compression metadata stored therein.

6. The apparatus of claim 5 , the processor to:
retrieve, from the first memory address, the data for the graphics workload; and
use the compression metadata to facilitate decompressing the data for the graphics in the first memory address in the first memory space.

7. A non-transitory machine readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to:
allocate a first memory space in a physical memory for data for a graphics workload, the first memory space comprising a first plurality of addressable physical memory locations;
allocate a second memory space in the physical memory for compression metadata relating to the data for the graphics workload, the compression metadata defining one or more elements of a compression technique used to compress the data for the graphics workload the second memory space comprising a second plurality of addressable physical memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space;
configure a direct memory mapping between the first plurality of addressable physical memory locations and the second plurality of addressable physical memory locations; and
repack the compression metadata in the second memory space using a hash function that relates a first physical addressable memory location in the second memory space to a second physical addressable memory location in the second memory space.

8. The non-transitory machine readable medium of claim 7 , wherein the predetermined ratio of the amount of memory allocated to the first memory space to the amount of memory in the second memory space is 256:1.

9. The non-transitory machine readable medium of claim 7 , further comprising instructions which configure the processor to:
receive a memory access request for the data for the graphics workload, the memory access request comprising a first memory address in the first memory space;
determine, from the first physical memory address, a second physical memory address in the second memory space; and
retrieve, from the second memory address, the compression metadata stored therein.

10. The non-transitory machine readable medium of claim 9 , further comprising instructions which configure the processor to:
retrieve, from the first memory address, the data for the graphics workload; and
use the compression metadata to facilitate decompression of the data for the graphics in the first memory address in the first memory space.

11. The non-transitory machine readable medium of claim 7 , further comprising instructions which configure the processor to:
receive a memory access request for the data for the graphics workload, the data access request comprising a first memory address in the first physical memory space;
determine, from the first memory address and the hash function, a second memory address in the second physical memory space; and
retrieve, from the second physical memory address, the compression metadata stored therein.

12. The non-transitory machine readable medium of claim 11 , further comprising instructions which configure the processor to:
retrieve, from the first memory address, the data for the graphics workload; and
use the compression metadata to facilitate decompressing the data for the graphics in the first memory address in the first memory space.

13. A computer-implemented method, comprising:
allocating a first memory space in a physical memory for data for a graphics workload, the first memory space comprising a first plurality of addressable physical memory locations;
allocating a second memory space in the physical memory for compression metadata relating to the data for the graphics workload, the compression metadata defining one or more elements of a compression technique used to compress the data for the graphics workload the second memory space comprising a second plurality of addressable physical memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space;
configuring a direct memory mapping between the first plurality of addressable physical memory locations and the second plurality of addressable physical memory locations; and
repacking the compression metadata in the second memory space using a hash function that relates a first physical addressable memory location in the second memory space to a second physical addressable memory location in the second memory space.

14. The method of claim 13 , wherein the predetermined ratio of the amount of memory allocated to the first memory space to the amount of memory in the second memory space is 256:1.

15. The method of claim 13 , further comprising:
receiving a memory access request for the data for the graphics workload, the memory access request comprising a first memory address in the first memory space;
determining, from the first physical memory address, a second physical memory address in the second memory space; and
retrieving, from the second memory address, the compression metadata stored therein.

Assignees

• Intel Corp

Inventors

• Cooray Niranjan L
• Koker Altug
• Krishnan Vidhya
• Silvas Ronald W
• Feit John H
• Surti Prasoonkumar
• Ray Joydeep
• Appu Abhishek R

Classifications

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/0837 Primary

  with software control, e.g. non-cacheable data · CPC title

• H04L9/0643

  Hash functions, e.g. MD5, SHA, HMAC or f9 MAC · CPC title

• G06T2200/28

  involving image processing hardware · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title